CS/ECE 552 Final Project Description
WISCFL06 Instruction Set Architecture
Instruction Format 
Syntax 
Semantics 
00000 xxxxxxxxxxx 
HALT 
Cease instruction issue, dump memory state to file 
00001 xxxxxxxxxxx 
NOP 
None 



01000 sss ddd iiiii 
ADDI Rd, Rs, immediate 
Rd < Rs + I(sign ext.) 
01001 sss ddd iiiii 
SUBI Rd, Rs, immediate 
Rd < I(sign ext.)  Rs 
01010 sss ddd iiiii 
XORI Rd, Rs, immediate 
Rd < Rs XOR I(zero ext.) 
01011 sss ddd iiiii 
ANDNI Rd, Rs, immediate 
Rd < Rs AND ~I(zero ext.) 
10100 sss ddd iiiii 
ROLI Rd, Rs, immediate 
Rd < Rs <<(rotate) I(lowest 4 bits) 
10101 sss ddd iiiii 
SLLI Rd, Rs, immediate 
Rd < Rs << I(lowest 4 bits) 
10110 sss ddd iiiii 
RORI Rd, Rs, immediate 
Rd < Rs >>(rotate) I(lowest 4 bits) 
10111 sss ddd iiiii 
SRLI Rd, Rs, immediate 
Rd < Rs >> I(lowest 4 bits) 
10000 sss ddd iiiii 
ST Rd, Rs, immediate 
Mem[Rs + I(sign ext.)] < Rd 
10001 sss ddd iiiii 
LD Rd, Rs, immediate 
Rd < Mem[Rs + I(sign ext.)] 
10011 sss ddd iiiii 
STU Rd, Rs, immediate 
Mem[Rs + I(sign ext.)] < Rd
Rs < Rs + I(sign ext.) 



11001 sss xxx ddd xx 
BTR Rd, Rs 
Rd[bit i] < Rs[bit 15i] for i=0..15 
11011 sss ttt ddd 00 
ADD Rd, Rs, Rt 
Rd < Rs + Rt 
11011 sss ttt ddd 01 
SUB Rd, Rs, Rt 
Rd < Rt  Rs 
11011 sss ttt ddd 10 
XOR Rd, Rs, Rt 
Rd < Rs XOR Rt 
11011 sss ttt ddd 11 
ANDN Rd, Rs, Rt 
Rd < Rs AND ~Rt 
11010 sss ttt ddd 00 
ROL Rd, Rs, Rt 
Rd < Rs << (rotate) Rt (lowest 4 bits) 
11010 sss ttt ddd 01 
SLL Rd, Rs, Rt 
Rd < Rs << Rt (lowest 4 bits) 
11010 sss ttt ddd 10 
ROR Rd, Rs, Rt 
Rd < Rs >> (rotate) Rt (lowest 4 bits) 
11010 sss ttt ddd 11 
SRL Rd, Rs, Rt 
Rd < Rs >> Rt (lowest 4 bits) 
11100 sss ttt ddd xx 
SEQ Rd, Rs, Rt 
if (Rs == Rt) then Rd < 1 else Rd < 0 
11101 sss ttt ddd xx 
SLT Rd, Rs, Rt 
if (Rs < Rt) then Rd < 1 else Rd < 0 
11110 sss ttt ddd xx 
SLE Rd, Rs, Rt 
if (Rs <= Rt) then Rd < 1 else Rd < 0 
11111 sss ttt ddd xx 
SCO Rd, Rs, Rt 
if (Rs + Rt) generates carry out
then Rd < 1 else Rd < 0 



01100 sss iiiiiiii 
BEQZ Rs, immediate 
if (Rs == 0) then
PC < PC + 2 + I(sign ext.) 
01101 sss iiiiiiii 
BNEZ Rs, immediate 
if (Rs != 0) then
PC < PC + 2 + I(sign ext.) 
01110 sss iiiiiiii 
BLTZ Rs, immediate 
if (Rs < 0) then
PC < PC + 2 + I(sign ext.) 
01111 sss iiiiiiii 
BGEZ Rs, immediate 
if (Rs >= 0) then
PC < PC + 2 + I(sign ext.) 
11000 sss iiiiiiii 
LBI Rs, immediate 
Rs < I(sign ext.) 
10010 sss iiiiiiii 
SLBI Rs, immediate 
Rs < (Rs << 8)  I(zero ext.) 



00100 ddddddddddd 
J displacement 
PC < PC + 2 + D(sign ext.) 
00101 sss iiiiiiii 
JR Rs, immediate 
PC < Rs + I(sign ext.) 
00110 ddddddddddd 
JAL displacement 
R7 < PC + 2 PC < PC + 2 + D(sign ext.) 
00111 sss iiiiiiii 
JALR Rs, immediate 
R7 < PC + 2 PC < Rs
+ I(sign ext.) 



00010 
Undefined 
produce IllegalOp exception 
00011 xxxxxxxxxxx 
NOP / RTI 
PC < EPC 
WISCSP06 supports instructions in four different formats: Jformat,
2 Iformats, and the Rformat. These are described below.
The Jformat is used for jump instructions that need a large displacement.
JFormat
5 bits 
11 bits 
Op Code 
Displacement 
Jump Instructions
The Jump instruction loads the PC with the value found by adding the PC of the
next instruction (PC+2, not PC+4 as in MIPS) to the signextended
displacement.
The JumpAndLink instruction loads the PC with the same value and also saves the
address of the next sequential instruction (i.e., PC+2) in the link register
R_{7}.
The syntax of the jump instructions is:

J displacement

JAL displacement
Iformat instructions use either a destination register, a source register,
and a 5bit immediate value; or a destination register and an 8bit immediate
value. The two types of Iformat instructions are described below.
Iformat 1 Instructions
Iformat 1
5 bits 
3 bits 
3 bits 
5 bits 
Op Code 
R_{s} 
R_{d} 
Immediate 
The Iformat 1 instructions include XORImmediate, ANDNImmediate, AddImmediate,
SubtractImmediate, RotateLeftImmediate, ShiftLeftLogicalImmediate,
ShiftRightArithmeticImmediate,
ShiftRightLogicalImmediate,
Load, Store, and Store with Update.
The ANDNI instruction loads register R_{d }with the value
of the register R_{s} ANDed with the one's complement of
the zeroextended immediate value. (It may be thought of as a bitclear
instruction.) ADDI
loads register R_{d} with the sum of the
value of the register R_{s} plus the signextended immediate
value.
SUBI loads register R_{d} with the result of subtracting
register R_{s} from the signextended immediate value.
(That is, immed  R_{s}, not R_{s}  immed.)
Similar instructions have similar semantics, i.e. the logical
instructions have zeroextended values and the arithmetic instructions
have signextended values.
For Load and Store instructions, the effective address of the operand
to be read or written is calculated by adding the value in register R_{s}
with the signextended immediate value. The value is loaded
to or stored from register R_{d}. The STU instruction, Store
with Update, acts like Store but also writes R_{s} with the effective address.
The syntax of the Iformat 1 instructions is:

ADDI R_{d}, R_{s}, immediate

SUBI R_{d}, R_{s}, immediate

XORI R_{d}, R_{s}, immediate

ANDNI R_{d}, R_{s}, immediate

ROLI R_{d}, R_{s}, immediate

SLLI R_{d}, R_{s}, immediate

RORI R_{d}, R_{s}, immediate

SRLI R_{d}, R_{s}, immediate

ST R_{d}, R_{s}, immediate

LD R_{d}, R_{s}, immediate

STU R_{d}, R_{s}, immediate
Iformat 2 Instructions
Iformat 2
5 bits 
3 bits 
8 bits 
Op Code 
R_{s} 
Immediate 
The Load Byte Immediate instruction loads R_{s} with a signextended 8 bit immediate value.
The ShiftandLoadByteImmediate instruction
shifts R_{s} 8 bits to the left, and replaces the lower 8 bits
with the immediate value.
The format of these instructions is:

LBI R_{s}, signed immediate

SLBI R_{s}, unsigned immediate
The JumpRegister instruction loads the PC with the value of register
R_{s} + signed immediate. The JumpAndLinkRegister instruction does the same
and also saves the return address (i.e., the address of the JALR instruction plus one)
in the link register R_{7}.
The format of these instructions is

JR Rs, immediate

JALR Rs, immediate
The branch instructions test a general purpose register for
some condition. The available conditions are: equal to zero, not equal
to zero, less than zero, and greater than or equal to zero.
If the condition holds, the signed immediate
is added to the address of the next sequential instruction
and loaded into the PC.
The format of the branch instructions is

BEQZ Rs, signed immediate

BNEZ Rs, signed immediate

BLTZ Rs, signed immediate

BGEZ Rs, signed immediate
Rformat instructions use only registers for operands.
Rformat
5 bits 
3 bits 
3 bits 
3 bits 
2 bits 
Op Code 
Rs 
Rt 
Rd 
Op Code Extension 
ALU and Shift Instructions
The ALU and shift Rformat instrucions are similiar to Iformat 1 instructions,
but do not require an immediate value. In each case, the value of
R_{t} is used in place of the immediate. No extension of
its value is required. In the case of shift instructions, all
but the 4 leastsignificant bits of R_{t} are ignored.
The ADD instruction performs signed addition.
The SUB instruction subtracts R_{s} from R_{t}.
(Not R_{s}  R_{t}.)
The set instructions SEQ, SLT, SLE instructions compare the values in
R_{s} and R_{t}
and set the destination register R_{d} to 0x1 if the comparison is
true, and 0x0 if the comparison is false.
SLT checks for R_{s} less than R_{t}, and
SLE checks for R_{s} less than or equal to R_{t}.
(R_{s} and R_{t} are two's complement numbers.)
The set instruction SCO will set R_{d} to 0x1 if
R_{s} plus R_{t} would generate a carryout from the most
significant bit; otherwise it sets R_{d} to 0x0.
The BitReverse instruction, BTR, takes a single operand R_{s} and
copies it to R_{d}, but with a leftright reversal of each bit;
i.e. bit 0 goes to bit 15, bit 1 goes to bit 14, etc.
The syntax of the Rformat ALU and shift instructions is:

ADD R_{d}, R_{s}, R_{t}

SUB R_{d}, R_{s}, R_{t}

ANDN R_{d}, R_{s}, R_{t}

ROL R_{d}, R_{s}, R_{t}

SLL R_{d}, R_{s}, R_{t}

ROR R_{d}, R_{s}, R_{t}

SRL R_{d}, R_{s}, R_{t}

SEQ R_{d}, R_{s}, R_{t}

SLT R_{d}, R_{s}, R_{t}

SLE R_{d}, R_{s}, R_{t}

SCO R_{d}, R_{s}, R_{t}

BTR R_{d}, R_{s}
Special instructions use the Rformat. The HALT instruction halts
the processor. The HALT instruction and all older instructions
execute normally, but the instruction after the halt will never
execute. The PC is left pointing to the instruction directly after
the halt.
The Nooperation instruction occupies a position in the pipeline, but does
nothing.
The syntax of these instructions is:
The RTI instruction should remain equivalent to NOP until the rest of
the design has been completed and thoroughly tested.
RTI returns from an exception by loading the PC from the value in the
EPC register.
The syntax of this instruction is:
