CS/ECE 752: Advanced Computer Architecture I

Fall 1999 Offering

Instructor Mark D. Hill and Teaching Assistant Collin McCurdy

Readings for Midterm 1

This reading list may be updated until the review before midterm 1.

Key for Locations

• (Bn) means in Chapter n of Hill, Jouppi, and Sohi's "Readings in Computer Architecture"
• (Wn) means in Chapter n of Hill, Jouppi, and Sohi's web component at URL http://www.mkp.com/architecture-readings/wc/
• (other) means not in either of the above.

H&P Chapter 1

• Arthur W. Burks, Herman H. Goldstine, John von Neumann. Preliminary discussion of the logical design of an electronic computing instrument, Report to the U.S. Army Ordinance Department, 1946. Reprinted as Chapter 4 of Bell and Newell, Computer Structures: Readings and Examples, McGraw-Hill, 1971. URL: Chapter 4 of http://www.research.microsoft.com/users/gbell/Computer_Structures__Readings_and_Examples/ (W1).

• Gordon Moore. Cramming More Components onto Integrated Circuits, Electronics, April 1965 (B1).

• Michael Slater. The Microprocessor Today, IEEE Micro, December 1996 (B10).

• Standard Performance Evaluation Corporation (SPEC). URL: http://www.specbench.org/ (W2). (Just skim as there is too much here to read carefully.)

• Transaction Processing Council (TPC). URL: http://www.tpc.org (W2). (Skim)

H&P Chapter 2

• William A. Wulf. Compilers and Computer Architecture, IEEE Computer, July 1981 (B3).

• Robert P. Colwell, Charles Y. Hitchcock, E. Douglas Jensen, H. M. Brinkey Sprunt, and Charles P. Kollar. Computers, Complexity, and Controversy, IEEE Computer, September 1985 (B3).

• Intel IA-32 Architecture Reference Shelf. URL: http://developer.intel.com/vtune/cbts/refman.htm (W3). (Skim)

• J. S. Emer and D. W. Clark. A Characterization of Processor Performance in the VAX-11/780, Proc. International Symposium on Computer Architecture , June 1984 (B2).

H&P Chapter 5

• Rambus Technology Overview. February 1999. URL: http://www.rambus.com/docs/techover.pdf (W6).

• D. Kroft. Lockup-Free Instruction Fetch/Prefetch Cache Organization, Proc. International Symposium on Computer Architecture , May 1981 (B6).

• Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proc. International Symposium on Computer Architecture , June 1990 (B6).

• Eric Rotenberg, Steve Bennett, J. E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. In Proceedings of International Symposium on Microarchitecture, pages 24-34, December 1996. URL: ftp://ftp.cs.wisc.edu/sohi/papers/1996/micro.trace-cache.ps.gz (W6).

• D. W. Clark and J. S. Emer. Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement, ACM Trans. on Computer Systems, February 1985 (B6).

• Madhusudhan Talluri and Mark D. Hill Surpassing the TLB Performance of Superpages with Less Operating System Support. In Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems, pages 171-182, October 1994. URL: ftp://ftp.cs.wisc.edu/markhill/Papers/asplos6_superpages.ps (W6).

• Wen-Hann Wang, Jean-Loup Baer, and Henry M. Levy. Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy, Proc. International Symposium on Computer Architecture , June 1989 (B6).