CS/ECE 752: Advanced Computer Architecture I

Fall 1999 Offering

Instructor Mark D. Hill and Teaching Assistant Collin McCurdy

Readings for Midterm 2

This reading list may be updated until the review before midterm 2.

Key for Locations

• (Bn) means in Chapter n of Hill, Jouppi, and Sohi's "Readings in Computer Architecture"
• (Wn) means in Chapter n of Hill, Jouppi, and Sohi's web component at URL http://www.mkp.com/architecture-readings/wc/
• (other) means not in either of the above.

H&P Chapter 3 and 4: Pipelining and ILP

• J. E. Smith. An Analysis of Pipeline Clocking, University of Wisconsin-Madison ECE Unpublished Note, March 1990. URL: http://www.ece.wisc.edu/~jes/752/misc/clocks.ps (web).

• J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors, IEEE Trans. on Computers, May 1988 (B4).

• T-Y. Yeh and Y. Patt. Two-level Adaptive Training Branch Prediction, Proc. 24th Annual International Symposium on Microarchitecture, Nov 1991 (B4).

• Gurindar S. Sohi and S. Vajapeyam. Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, Proc. 14th Annual Symposium in Computer Architecture, June 1987 (B4).

• Kenneth C. Yeager. The MIPS R10000 Superscalar Microprocessor, IEEE Micro, April 1996 (B4).

• D. Papworth. Tuning the Pentium Pro Architecture, IEEE Micro, April 1996 (B10).

• M. H. Lipasti and J. P. Shen. Exceeding the Dataflow Limit via Value Prediction, Proc. 29th Annual International Symposium on Microarchitecture, December 1996. URL: http://www.ece.cmu.edu/~mhl/www/micro29.ps.gz (W4).

• Richard M. Russell. The Cray-1 Computer System, Communications of the ACM, January 1978 (B1).

• Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Proc. 23rd Annual International Symposium on Computer Architecture, May 1996 (B5).

• B. Ramakrishna Rau and Joseph A. Fisher Instruction-Level Parallel Processing: History, Overview and Perspective, Journal of Supercomputing, 1993 (B4) (skim).

• Intel IA-64 Architecture. URL: http://developer.intel.com/design/ia64/architecture.htm (W3) (skim).

• G. S. Sohi, S. E. Breach and T.N. Vijaykumar. Multiscalar Processors, Proc. 22nd Annual International Symposium on Computer Architecture , June 1995. URL: ftp://ftp.cs.wisc.edu/sohi/papers/1995/isca.multiscalar.ps (W4).

H&P Chapter 6: Storage

• Hill, Jouppi, and Sohi. Three Simple but Useful Models, Section 2.3.1 of Introduction to Methods, Readings in Computer Architecture, 2000 (B2).

• C. Ruemmler and J. Wilkes. An introduction to Disk Drive Modeling, IEEE Computer, March 1994 (B7) (skim).

• David A. Patterson, Garth Gibson, and Randy H. Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID), Proc. ACM SIGMOD Conference, June 1988 (B7).

H&P Chapter 7: Networks

• R. M. Metcalfe and D. R. Boggs. Ethernet: Distributed Packet Switching for Local Computer Networks, Communications of the ACM, July 1975 (B7).

• Richard B. Gillett. Memory Channel Network for PCI, IEEE Micro, February 1996 (hardcopy handout).

• K. Akerly. Reality Engine Graphics, Proc. SIGGRAPH, 1993 (B7).