CS/ECE 752 Advanced Computer Architecture I Fall 2004 Section 1 Instructor Mark D. Hill and T. A. Andrey Litvin URL: http://www.cs.wisc.edu/~markhill/cs752/Fall2004/

Homework 1 // Due at Lecture Tue Sep 21

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition, 2002.

Disclaimer: Too avoid being too much work, homeworks only sample course material. Exams also sample course material and will include questions on material not covered in homeworks. Homeworks will tend to cover material related to the text, reviews focus on papers, and exams on both.

Problem 1 (8 points)

H&P Problem 1.2.

Problem 2 (4 points)

A computer C can use one of two mythical Intel IA-32 processors P10 and P11. P10 uses a 8-stage pipeline clocked at 2 GHz, while P11 uses a 12-stage pipeline clocked at 4 GHz. Both have identical on-chip memory hierarchies.

Give two different reasons why computer C with processor P11 is not likely to be twice as fast as computer C with processor P10.

Problem 3 (8 points)

H&P Problem 2.6.

Problem 4 (4 points)

As transistor sizes become smaller with technology, the electrical charge they hold lessens.  As a result, logic devices, such as SRAMS, gates, and latches, become more sensitive to random alpha particle and neutron particle strikes that can hit a transistor and invert the state of the logic device.

Such transient errors are a serious unpredictable threat to the correct execution of a program.   However, some storage cells that are affected by transient faults will inevitably not affect the correct execution of a program.  For example, if a strike occurs to the storage cell of a NOP instruction's unused operand field (and not its opcode field), the error will not affect the correct-path instruction execution.  Determining the susceptibility of a logic device to these strikes is helpful to microprocessor designers gauging the amount of error protection/correction the processor needs for reliable behavior.

Researchers have defined the following terms related to characterizing faults:

• An Architectually Correct Execution (ACE) instruction is an instruction whose results may potentially affect the output of the program and thus it is imperative particle strikes do not negatively alter the instruction's encoding.

• The Architectual Vulnerability Factor (AVF), is the fraction of time an ACE instruction is present in a logic device.

A given system has a 64-entry Instruction Queue.  From observation, two instructions are fetched (on average) each cycle and remain in the queue for an average of 18 cycles.  One out of every 4 instructions are ACE instructions.  What is the average AVF of a single instruction queue entry?

Problem 5 (6 points)

Most personal computers (PCs) use microprocessors from AMD or Intel that execute the IA-32 (a.k.a. x86) instruction set architecture. This architecture is limited to 32-bit virtual addresses (or 2^32 = 4GBytes of virtual memory per process). Since this limit is already inadequate for medium-to-large servers and will be inadequate for more future systems, AMD--and recently Intel--have introduced extensions to IA-32/x86 that enable 64-bit addressing.

In two-three paragraphs, summarize the basic ideas behind these x86 64-bit extensions. Since AMD's and Intel's versions are similar, you may choose to discuss either company's version.

Note 1: This is information is not in your text or assigned readings.

Note 2: This question is not about Itanium (IA-64) that is an instruction set architecture completely different from x86.