CS/ECE 752 Advanced Computer Architecture I Fall 2004 Section 1 Instructor Mark D. Hill and T. A. Andrey Litvin URL: http://www.cs.wisc.edu/~markhill/cs752/Fall2004/

Homework 4 // Due at Lecture Thu November 18

Problem 1 (10 points)

H&P Problem 5.4abcde (not f)

Problem 2 (6 points)

H&P Problem 5.17

Problem 3 (6 points)

Consider a computer that implements paged virtual memory with 64-bit virtual addresses, 44-bit physical addresses, 8K-byte pages, and 8-bit address space identifiers.

Assume it uses a 128K-byte L1 data cache with two-way set-associativity, LRU replacement, 128-byte blocks, and write-back.

(a) Let the data cache be accessed logically after address translation. Exactly which bits need to stored in a block's tag? What other bits (e.g., state bits) need to be stored with each block?

(b) Repeat part (a) assuming instead that the data cache is accessed logically before address translation and need not be flushed on most context switches.

Problem 4 (6 points)

Assume that person arrives at an automatic teller machine (ATM) about once every 60 seconds and each person uses the ATM for an average of 50 seconds. (Hint: See H&P Section 7.8).

(a) Without additional assumptions, can you calculate the utilization of the ATM (the fraction of time it is busy)? If so, what is the utilization? If not, what other things do you need to know?

(a) Without additional assumptions, can you calculate the average queueing time for people arriving at the ATM (average time from when a person arrives to when she begins using the ATM)? If so, what is the average queueing time? If not, what other things do you need to know?