CS/ECE 752 Advanced Computer Architecture I Fall 2004 Section 1
Instructor Mark D. Hill and T. A. Andrey Litvin
URL: http://www.cs.wisc.edu/~markhill/cs752/Fall2004/

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition, 2002.

HJ&S is Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000.

Fundamentals of Computer System Design

H&P Chapter 1.

Gordon E. Moore, Cramming More Components onto Integrated Circuits, Electronics, April 1965. Reprinted in HJ&S pp. 56-59.

ITRS Roadmap -- Executive Summary, URL http://public.itrs.net/Files/2003ITRS/ExecSum2003.pdf, 75 pages. Read Introduction (pp. 1-10) and flip through Grand Challenges (pp. 11-17), reading, at least, titles.

Standard Performance Evaluation Corporation (SPEC). URL: http://www.specbench.org/ (reference).

Transaction Processing Council (TPC). URL: http://www.tpc.org (reference).

Arthur W. Burks, Herman H. Goldstine, John von Neumann. Preliminary discussion of the logical design of an electronic computing instrument, Report to the U.S. Army Ordinance Department, 1946. Reprinted as Chapter 4 of Bell and Newell, Computer Structures: Readings and Examples, McGraw-Hill, 1971. URL: Chapter 4 of http://www.research.microsoft.com/users/gbell/Computer_Structures__Readings_and_Examples/ (reference).

Instruction Set Principles and Examples

H&P Chapter 2.

William A. Wulf. Compilers and Computer Architecture, IEEE Computer, July 1981. Reprinted in HJ&S pp. 119-125.

J. S. Emer and D. W. Clark. A Characterization of Processor Performance in the VAX-11/780, Proc. International Symposium on Computer Architecture , June 1984. Reprinted in HJ&S pp. 101-110.

IA-32 Intel(R) Architecture Software Developer's Manual, Volume 1: Basic Architecture. URL: http://www.intel.com/design/pentium4/manuals/25366514.pdf, 448 pages (reference).

Instruction-Level Parallelism and Its Dynamic Exploitation

H&P Appendix A reviews pipeline background material from CS/ECE 552.

H&P Chapter 3.

J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors, IEEE Trans. on Computers, May 1988. Reprinted in HJ&S pp. 202-213.

T-Y. Yeh and Y. Patt. Two-level Adaptive Training Branch Prediction, Proc. 24th Annual International Symposium on Microarchitecture, Nov 1991. Reprinted in HJ&S pp. 228-237.

Kenneth C. Yeager. The MIPS R10000 Superscalar Microprocessor, IEEE Micro, April 1996. Reprinted in HJ&S pp. 275-287.

Gurindar S. Sohi and S. Vajapeyam. Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, Proc. 14th Annual Symposium in Computer Architecture, June 1987 (reference). Reprinted in HJ&S pp. 244-251.

D. Papworth. Tuning the Pentium Pro Architecture, IEEE Micro, April 1996. Reprinted in HJ&S pp. 660-667.

E. Borch, E. Tune, S. Manne, and J. Emer, Loose Loops Sink Chips, Proceedings of HPCA-8, February 2002. Online PDF for University of Wisconsin only.

Simcha Gochman, Ronny Ronen, Ittai Anati, Ariel Berkovits, Tsvika Kurts, Alon Naveh, Ali Saeed, Zeev Sperber, Robert C. Valentine, The Intel (R) Pentium(R) M Processor: Microarchitecture and Performance Intel Technology Journal, May 2003. Online PDF.

Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Proc. 23rd Annual International Symposium on Computer Architecture, May 1996. Reprinted in HJ&S pp. 350-361.

Onur Mutlu and Jared Stark and Chris Wilkerson and Yale N. Patt, Runahead Execution: An Effective Alternative to Large Instruction Windows, IEEE Micro, Nov/Dec 2003. Online PDF for University of Wisconsin only.