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Homework 3 // Due at Lecture Wed Oct 12
Problem 1 (15 points)
Do the example from H&P page 108, but use the following code fragment
rather than the one given:
| | L.D | F6,32(R2) |
| | L.D | F2,44(R3) |
| | MUL.D | F0,F2,F4 |
| | SUB.D | F8,F6,F2 |
| A | DIV.D | F10,F0,F6 |
| | ADD.D | F6,F8,F2 |
| B | SUB.D | F2,F10,F8 |
| | L.D | F6,40(R2) |
| | MUL.D | F0, F2, F4 |
| | SUB.D | F8,F6,F2 |
Assume the same latencies for floating point as in the example. Assume the latency for loads is 2 cycles.
What cycle will A be ready to commit? Show the status tables for that cycle (formatted like in Figure 2.15). Do the same for B.
Problem 2 (15 points)
(This problem is important well beyond the points we assign to it,
because it continues our gentle ramp for teaching you about simulators,
in general, and SimpleScalar, in particular.)
For this problem you will be implementing the
3-bit branch prediction scheme.
A 3-bit branch prediction scheme consists of eight states, and is a logical extension of a 2-bit branch predictor.
When a branch is taken, the predictor, the predictor switches to the next more strongly taken state (unless it is
already saturated); when it is not taken, it switches to the next more weakly taken state.
a) Edit bpred.h and bpred.c to support the 3-bit prediction scheme.
(It is probably easiest to just modify an existing predictor rather than adding a new one). Initialize all
counters to very weakly taken.
b) Using sim-outorder, run the 3-bit prediction scheme
with sim-outorder's default configuration. For crafty, gcc, and mcf,
fast-forward for 50M instructions and then run for 100M instructions each.
Similarly, run the built-in perfect, bimod and 2 lev prediction schemes.
Compare and comment on your results of the three
policies in terms of IPC and Miss Rate at
the L1 and the L2 Cache.
c) Include a print-out of the changes to
bpred.c and bpred.h with
your changes highlighted. Please document your changes.
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