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Homework 4 // Due at Lecture Wed Oct 26
Problem 1 (6 points)
H&P, 4th Edition, Question 5.2 a,b,c, but use 45nm technology rather than 90nm. As stated in Question 5.1, assume 64-byte blocks.
Problem 2 (9 points)
Consider a virtual memory system with the following properties:
- 55 bit virtual address (byte addressable)
- 8-KByte pages
- 45 bit physical byte addresses
- 64 GBytes of physical memory
- 4 MByte cache that is 8-way set-associative and is accessed with physical addresses
- a 64 entry TLB
- 64-byte blocks
- What is the total size of the page table for each process on this machine, assuming that the valid, protection, dirty, and use
bits take a total of 4 bits, and that all of the virtual pages are in use? (Assume that disk addresses are not stored in the page table). Calculate both the minimum number of bits needed to hold the information and the "typical" storage assuming a page table entry is rounded up to the next power of two number of bytes.
- Draw a diagram of the hardware in the memory system including the cache and TLB. Make sure you show how different
fields of the address (i.e. which bits) are used to access the cache and TLB. Use Figure C.24 in H&P as a model for your
diagram.
- Explain how a memory access proceeds through the memory system for each of the following scenarios: cache hit, cache
miss, TLB hit, and TLB miss.
Problem 3 (5 points)
Caches can be either virtually or physically indexed, and either virtually or physically tagged. That is, there are four possible combinations: VI-VT, VI-PT, PI-VT, and PI-PT. Briefly explain the advantages and disadvantages of each of these.
Problem 4 (8 points)
The following code segment, consisting of six instructions, needs to be executed 64 times
for the evaluation of vector arithmetic expression: D(I)= A(I)+B(I)*C(I)
for 0<=I<=63:
load r1, B(i)
load r2, C(i)
mul r1,r1,r2
load r3, A(i)
add r3,r3,r1
store D(i), r3
where r1, r2, and r3 are CPU registers. Assume five cycles for each load or store, three cycles for add,
and nine cycles for multiply on either a uniprocessor or a single PE in a SIMD machine.
- Calculate the total number of CPU cycles needed to execute the above code 64 times
on an in-order uniprocessor, ignoring all other delays.
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Consider using a SIMD prcoessor with 64 PEs to execute the above vector operations
in six synchronized vector instructions over 64-component vector data and both driven
by the same-speed clock. Calculate the total execution time on the SIMD machine,
ignoring instruction broadcast and other delays.
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What is the speedup of the SIMD processor over the uniprocessor?
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