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Reader 1This reader may still change slightly, and, if so, I will send email notice of changes. H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition, 2002. HJ&S is Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000. Technology, Cost, Performance, Power, etc.H&P Chapter 1. Gordon E. Moore, Cramming More Components onto Integrated Circuits, Electronics, April 1965. Reprinted in HJ&S pp. 56-59. ITRS Roadmap -- Executive Summary, Go to URL http://www.itrs.net/Common/2005ITRS/Home2005.htm and click on href="http://www.itrs.net/Common/2005ITRS/ExecSum2005.pdf"> Executive Summary, 89 pages. Read Introduction (pp. 1-10) and flip through Grand Challenges (pp. 11-18), reading, at least, titles. David A. Patterson, Latency lags bandwith, Communications of the ACM, October 2004. Online PDF for University of Wisconsin only. Standard Performance Evaluation Corporation (SPEC). URL: http://www.specbench.org/ (reference). Transaction Processing Council (TPC). URL: http://www.tpc.org (reference). Instruction SetsH&P Chapter 2. William A. Wulf. Compilers and Computer Architecture, IEEE Computer, July 1981. Reprinted in HJ&S pp. 119-125. J. S. Emer and D. W. Clark. A Characterization of Processor Performance in the VAX-11/780, Proc. International Symposium on Computer Architecture , June 1984. Reprinted in HJ&S pp. 101-110. IA-32 Intel(R) Architecture Software Developer's Manual, Volume 1: Basic Architecture. Online PDF for University of Wisconsin only., 476 pages (reference). CachesH&P Chapter 5.1-5.7 Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proc. International Symposium on Computer Architecture , June 1990. Reprinted in HJ&S pp. 395-404. David H. Albonesi, Selective Cache Ways: On-demand Cache Resource Allocation, Proc. International Symposium on Microarchitecture (MICRO), 1999. Online PDF for University of Wisconsin only. Changkyu Kim, Doug Burger, and Stephen W. Keckler. An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches, Proc. Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002. Online PDF for University of Wisconsin only. MemoryH&P Chapter 5.8 - 5.18 (skip Pentium example in 5.11 and skim 5.14, 5.15, & 5.18) The PC Guide: DRAM Technologies, http://www.pcguide.com/ref/ram/tech.htm URL http://www.pcguide.com/ref/ram/tech.htm and ten Next pages (reference). Peter Vogt, Fully Buffered DIMM Server Memory Architecture, Talk at Intel Developers Forum, Feb. 2004. Online PDF for University of Wisconsin only. Bruce Jacob and Trevor Mudge. Virtual Memory on Contemporary Processors, IEEE Micro, vol. 18, no. 4, 1998. Online PDF for University of Wisconsin only. Wen-Hann Wang, Jean-Loup Baer, and Henry M. Levy. Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy, Proc. International Symposium on Computer Architecture , June 1989. Reprinted in HJ&S pp. 434-442. MiscellaneousArthur W. Burks, Herman H. Goldstine, John von Neumann. Preliminary discussion of the logical design of an electronic computing instrument, Report to the U.S. Army Ordinance Department, 1946. Reprinted as Chapter 4 of Bell and Newell, Computer Structures: Readings and Examples, McGraw-Hill, 1971. URL: Chapter 4 of http://www.research.microsoft.com/users/gbell/Computer_Structures__Readings_and_Examples/ (reference). Timothy J. Slegel, et al., IBM's S/390 G5 Microprocessor, IEEE Micro, Mar/Apr 1999, Online PDF for University of Wisconsin only. |
