CS/ECE 752 Advanced Computer Architecture I Spring 2006 Section 1
Instructor Mark D. Hill and T. A. Ahmed Ghanem
URL: http://www.cs.wisc.edu/~markhill/cs752/Spring2006/

This reader may still change slightly, and, if so, I will send email notice of changes.

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition, 2002.

HJ&S is Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000.

Pipelining

H&P Appendix A reviews pipeline background material from CS/ECE 552.

T-Y. Yeh and Y. Patt. Two-level Adaptive Training Branch Prediction, Proc. 24th Annual International Symposium on Microarchitecture, Nov 1991. Reprinted in HJ&S pp. 228-237.

Dan Ernst, et al., A Low-Power Pipeline Based on Circuit-Level Timing Speculation, Proc. 36th Annual International Symposium on Microarchitecture, 2003 Online PDF for University of Wisconsin only.

Multiple Issue and Static Scheduling

H&P Chapter 4.1, 4.2, 4.3, 4.5, and 4.7

C. McNairy and D. Soltis, Itanium 2 Processor Microarchitecture, IEEE Micro, Mar-Apr 2003, pp. 44-55. Online PDF for University of Wisconsin only.

Intel (R) Itanium (R) Architecture Software Development Manual, URL: http://www.intel.com/design/itanium/manuals/iiasdmanual.htm. See especially Volume 1's (Application Architecture) Chapter 4 (Application Programming Model), 36 pages (reference).

Dynamic Scheduling I and II

H&P Chapter 3 (but it is too long)

J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors, IEEE Trans. on Computers, May 1988. Reprinted in HJ&S pp. 202-213.

Kenneth C. Yeager. The MIPS R10000 Superscalar Microprocessor, IEEE Micro, April 1996. Reprinted in HJ&S pp. 275-287.

Gurindar S. Sohi and S. Vajapeyam. Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, Proc. 14th Annual Symposium in Computer Architecture, June 1987 (reference). Reprinted in HJ&S pp. 244-251.

D. Papworth. Tuning the Pentium Pro Architecture, IEEE Micro, April 1996. Reprinted in HJ&S pp. 660-667.

E. Borch, E. Tune, S. Manne, and J. Emer, Loose Loops Sink Chips, Proceedings of HPCA-8, February 2002. Online PDF for University of Wisconsin only.

Simcha Gochman, Ronny Ronen, Ittai Anati, Ariel Berkovits, Tsvika Kurts, Alon Naveh, Ali Saeed, Zeev Sperber, Robert C. Valentine, The Intel (R) Pentium(R) M Processor: Microarchitecture and Performance Intel Technology Journal, May 2003. Online PDF.

Onur Mutlu and Jared Stark and Chris Wilkerson and Yale N. Patt, Runahead Execution: An Effective Alternative to Large Instruction Windows, IEEE Micro, Nov/Dec 2003. Online PDF for University of Wisconsin only.

Vectors

H&P Appendix G: Vector Processors. URL http://books.elsevier.com/companions/1558605967/appendices/1558605967-appe ndix-g.pdf.

Richard M. Russell. The Cray-1 Computer System, Communications of the ACM, January 1978. Reprinted in HJ&S pp. 40-49.

Storage

H&P Chapter 7.7-7.8, 7.10

David A. Patterson, Garth Gibson, and Randy H. Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID), Proc. ACM SIGMOD Conference, June 1988 David A. Patterson, Garth Gibson, and Randy H. Katz. A Case for Redundant Arrays of Inexpensive Disks (RAID), Proc. ACM SIGMOD Conference, June 1988. Reprinted in HJ&S pp. 474-481.

Multithreading and Multiprocessors

H&P Chapter 6.9

Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Proc. 23rd Annual International Symposium on Computer Architecture, May 1996. Reprinted in HJ&S pp. 350-361.

H&P Chapter 6 Sections 6.1, 6.3, & 6.8.

Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, March-April 2005, pp. 21-29. Online PDF for University of Wisconsin only.

James Laudon, UltraSPARC T1: A 32-threaded CMP for Servers, Talk to Wisconsin CS/ECE 757 Class, March 30, 2006 (reference). Online PDF for University of Wisconsin only.

Miscellaneous

John Owens, Streaming Architectures and Technology Trends (Chapter 29) GPU Gems 2, Nvidia Web Page, 2005. Online PDF.

Emmett Kilgariff and Randima Fernando. The GeForce 6 Series GPU Architecture (Chapter 30) GPU Gems 2, Nvidia Web Page, 2005 (reference). Online PDF.

Matthew Adiletta, Mark Rosenbluth, Debra Bernstein, Gilbert Wolrich, and Hugh Wilkinson. The Next Generation of Intel IXP Network Processors, Intel Technical Journal (ITJ), Volume 6, Issue 3, August 15, 2002 (reference). Online PDF.