CS/ECE 752 Advanced Computer Architecture I Spring 2009 Section 1 Instructor Mark D. Hill and T. A. Arkaprava Basu URL: http://www.cs.wisc.edu/~markhill/cs752/Spring2009/

Homework 1 // Due at Lecture Mon Feb 2

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Fourth Edition, 2007.

Disclaimer: To avoid being too much work, homeworks only sample course material. Exams also sample course material and will include questions on material not covered in homeworks. Homeworks will tend to cover material related to the text, reviews focus on papers, and exams on both.

Problem 1 (12 points)

H&P Problem 1.12.a-d (Page 61).

Problem 2 (4 points)

The Wisconsin Architecture Research group has decided to roll out their own processor called The Wisconsin Mendota. Calculate the expected yield of the newly designed chip using (all or some of the) following data.

Die size : 370 mm^2
Estimated defect rate : 0.70 per cm^2
Manufacturing size : 90 nm
Transistors : 281 million
Alpha : 4

Problem 3 (4 points)

As transistor sizes become smaller with technology, the electrical charge they hold lessens.  As a result, logic devices, such as SRAMS, gates, and latches, become more sensitive to random alpha particle and neutron particle strikes that can hit a transistor and invert the state of the logic device.

Such transient errors are a serious unpredictable threat to the correct execution of a program.   However, some storage cells that are affected by transient faults will inevitably not affect the correct execution of a program.  For example, if a strike occurs to the storage cell of a NOP instruction's unused operand field (and not its opcode field), the error will not affect the correct-path instruction execution.  Determining the susceptibility of a logic device to these strikes is helpful to microprocessor designers gauging the amount of error protection/correction the processor needs for reliable behavior.

Researchers have defined the following terms related to characterizing faults:

• An Architectually Correct Execution (ACE) instruction is an instruction whose results may potentially affect the output of the program and thus it is imperative particle strikes do not negatively alter the instruction's encoding.

• The Architectual Vulnerability Factor (AVF), is the fraction of time an ACE instruction is present in a logic device.

A given system has a 64-entry Instruction Queue.  From observation, two instructions are fetched (on average) each cycle and remain in the queue for an average of 14 cycles.  One out of every 4 instructions are ACE instructions.  What is the average AVF of a single instruction queue entry?

Problem 4 (4 points)

Suppose there is some digital magic box that can do some processing on a stream of data. Assume that you may increase/decrease the frequency at which this magic box operates. Now, there is a stream of data arriving at constant rate and there is initially one magic box that is to operate on this stream of data to do something ( No need to worry about what it actually does). After sometime you get another digital magic box of exactly same characteristics as the previous one from one of your friend. So now you decide to use both of these two digital magic boxes to operate cooperatively, such that each one picks up alternating piece data from the incoming stream to operate on. Given this scenario, answer the following questions

(a) Considering only dynamic power dissipation, how does power consumption changes for each of these two boxes when you use two magic boxes instead of one, to operate on the data stream arriving at same constant rate? Also, what is the effect on aggregate dynamic power consumption when using two boxes?
(b) Now considering only the static power disspation answer the above question.

Problem 5 (4 points)

China has been working on its own processor design with its own ISA. Recently they have unveiled China Godson-3 processor. Answer the following question about that processor.

(a) Briefly explain what type of ISA they use in the processor.
(b) In three or four sentences explain how they plan to provide x86 ISA support on this new machine?

NOTE: Answering this question may require you to read few things that are not directly covered in the course material