CS/ECE 752 Advanced Computer Architecture I Spring 2009 Section 1 Instructor Mark D. Hill and T. A. Arkaprava Basu URL: http://www.cs.wisc.edu/~markhill/cs752/Spring2009/

Homework 4 // Due at Lecture Mon Mon Mar 9

Problem 1 (6 points)

H&P, 4th Edition, Question 5.2 a,b,c

Problem 2 (9 points)

Consider a virtual memory system with the following properties:

• 53 bit virtual address (byte addressable)
• 4-KByte pages
• 41-bit physical byte addresses
• 64GBytes of physical memory
• 2-MByte cache that is 8-way set-associative and is accessed with physical addresses
• a 64 entry TLB

1. What is the total size of the page table for each process on this machine, assuming that the valid, protection, dirty, and use bits take a total of 4 bits, and that all of the virtual pages are in use? (Assume that disk addresses are not stored in the page table). Calculate both the minimum number of bits needed to hold the information and the "typical" storage assuming a page table entry is rounded up to the next power of two number of bytes.
2. Draw a diagram of the hardware in the memory system including the cache and TLB. Make sure you show how different fields of the address (i.e. which bits) are used to access the cache and TLB. Use Figure C.24 in H&P as a model for your diagram.
3. Explain how a memory access proceeds through the memory system for each of the following scenarios: cache hit, cache miss, TLB hit, and TLB miss.

Problem 3 (9 points)

The following code segment, consisting of six instructions, needs to be executed 64 times 
for the evaluation of vector arithmetic expression: D(I)= A(I)+B(I)*C(I) 
for 0<=I<=63:
	load r1, B(i)
	load r2, C(i)
	mul r1,r1,r2
	load r3, A(i)
	add r3,r3,r1
	sto D(i), r3
where r1,r2, and r3 are CPU registers. Assume four cycles for each load or store, two cycles for add, 
and eight cycles for multiply on either a uniprocessor or a single PE in an SIMD machine.

	a) Calculate the total number of CPU cycles needed to execute the above code 64 times 
	on an in-order uniprocessor, ignoring all other delays.
	
	b) Consider using an SIMD prcoessor with 64 PEs to execute the above vector operations 
	in six synchronized vector instructions over 64-component vector data and both driven 
	by the same-speed clock.Calculate the total execution time on the SIMD machine, 
	ignoring instruction broadcast and other delays.

	c) What is the speedup gain of the SIMD processor over the uniprocessor one?
	

	

Problem 4 ( 4 points )

Explain in short, the comparative advantages/dis-advantages of FB-DIMM memory technology over DDR2/DDR3 technology.