Reading List
Last updated on
Monday, 05-Jan-2004 16:27:54 CST
Level Key
- Text: Chapters of Culler and Singh's
"Parallel Computer Architecture: A Hardware/Software Approach"
- L1: Level-one papers should be read in detail
(and will be covered on exams accordingly).
- L2: Level-two papers should be read to obtain their gist
(and will be covered on exams accordingly).
- L3: Level-three papers are for your information
(and will not be covered on exams).
Location Key
- (Bn) means in Chapter n of Hill, Jouppi,
and Sohi's "Readings in Computer Architecture"
- (Wn) means in Chapter n of Hill, Jouppi,
and Sohi's web component at URL
http://www.mkp.com/architecture-readings/wc/
- (other) means neither of the above.
Tentative Readings for Exam I
Introduction
- Text: Chapter 1 (start soon!)
- L2: Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi,
Introduction to Chapter 9 "Multiprocessors and Multicomputers," from
Readings in Computer Architecture, Morgan Kaufmann,
2000 (B9). This seven-page introduction presents a higher-level
view of where we are going than our text's Chapter 1.
Parallel Programming
- Text: Chapters 2, 3, 4. We will cover Chapter 2, 3, and 4 less carefully,
so you should read them for big picture issues,
not every detail. You will not be tested, for example,
on details on how a SPLASH benchmark works. Thus,
you need only skim Sections 3.5. Similarly, Section 4.4
is way too detailed.
- L1:
Luiz Andre Barroso, Kourosh Gharachorloo, and Edward Bugnion,
Memory System Characterization of Commercial Workloads,
Proc. International Symposium on Computer Architecture,
June 1998 (other:
pdf).
- L3:
Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi,
Chapter 2 "Methods" from
Readings in Computer Architecture Web Component, Morgan Kaufmann,
2000 (W2: html). This chapter points to several good resources,
including benchmarks and simulators.
Symmetric Multiprocessors 1
- Text: Chapter 5. On the first pass, skim Section 5.2, but read it
more carefully after we cover memory consistency model issues.
You can read Section 5.6. for just big picture issues.
- Text: Section 7.9 (Synchronization)
- L1:
Leslie Lamport,
How to Make a Multiprocessor Computer that Correctly
Executes Multiprocess Programs,
IEEE Tran. on Computers,
September 1979, pp. 690-691 (B9).
- L3:
Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi,
Chapter 9 "Multiprocessors and Multicomputers," from
Readings in Computer Architecture Web Component, Morgan Kaufmann,
2000 (W9: html).
Symmetric Multiprocessors 2
- Text: Chapter 6, except don't worry about minor details of case
studies in Section 6.5.
- L1:
Alan Charlesworth.
Starfire: Extending the SMP Envelope,
IEEE Micro,
January/February 1998, pp. 39-49
(W9: pdf)
.
- L2
Ravi Rajwar and James R. Goodman,
Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution,
Proc. 34th Intl. Symposium on Microarchitecture,
December 2001 (other:
pdf).
- L2:
William A. Wulf and Samuel P. Harbison,
Reflections in a pool of processors/An experience report on C.mmp/Hydra,
Proc. Nation Computer Conference (AFIPS),
June 1978 (B9).
Tentative Readings for Exam II
Scalable Multiprocessors
- Text: Chapter 7, except Section 7.8
- L1:
Thorsten von Eicken, David E. Culler, Seth C. Goldstein and Klaus E. Schauser,
Active Messages: a Mechanism for Integrating Communication and Computation,
Proc. 19th Annual Symposium on Computer Architecture,
May 1992 (other:
ps).
- L1:
Steven L. Scott,
Synchronization and Communication in the T3E Multiprocessor,
Proceedings of International Conference on
Architectural Support for Programming Languages and Operating Systems,
pages 26-36, October 1996
(W9: pdf).
Distributed Shared Memory 1
- Text: Chapter 8
- L1:
James Laudon and Daniel Lenoski
The SGI Origin: A ccNUMA Highly Scalable Server.
In Proceedings of International Symposium on Computer Architecture,
pages 241-251, June 1997
(W9: pdf).
- L1:
Sarita V. Adve and Kourosh Gharachorloo,
Shared Memory Consistency Models: A Tutorial,
IEEE Computer,
29(12):66-76, December 1996
(W9: ps).
- L1:
Mark D. Hill,
Multiprocessors Should Support Simple Memory Consistency Models,
IEEE Computer,
August 1998
(W9: pdf).
- L2:
Luiz Andre Barroso, Kourosh Gharachorloo, Robert McNamara,
Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith,
Robert Stets, and Ben Verghese.
Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing,
Proc. International Symposium on Computer Architecture,
June 2000, pp. 282-293.
(W9: pdf).
- L2:
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood,
Bandwidth Adaptive Snooping,
Proc. High Performance Computer Architecture,
February 2002
(other: pdf).
- L3:
Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Wolf-Dietrich Weber,
Anoop Gupta, John Hennessy, Mark Horowitz, and Monica Lam.
The Stanford DASH Multiprocessor,
IEEE Computer,
March 1992, pp. 63-79 (B9).
Distributed Shared Memory 2
- Text: Chapters 9 and 11, but need only know the gist of
Sections 11.4.3, 11.6.3, 11.7.1-11.7.5, & 11.8
- L1:
Erik Hagersten, Anders Landin, and Seif Haridi,
DDM--A Cache-Only Memory Architecture,
IEEE Computer,
September 1992 pp. 44-54 (B9).
- L1:
Kai Li and Paul Hudak
Memory Coherence in Shared Virtual Memory Systems,
ACM Tran. on Computer Systems,
November 1989, pp. 321-359 (B9).
- L3
Erik Hagersten, Ashley Saulsbury, and Anders Landin,
Simple COMA Nodes Implmentations,
Proc. Hawaii Intl. Conf. on System Science,
January 1994 (other: Goto CS and view with
gv /afs/cs.wisc.edu/p/multifacet/extpapers/sun/scoma_hawaii94.ps
since I don't have permission to put it on the web).
- L3
Erik Hagersten and Michael Koster,
WildFire: A Scalable Path for SMPs,
Proc. High-Performance Computer Architecture,
January 1999 (other: Goto CS and view with
gv /afs/cs.wisc.edu/p/multifacet/extpapers/sun/wildfire-hpca99.ps
since I don't have permission to put it on the web).
Interconnection Networks
- Text: Chapter 10
- L2:
Philip Buonadonna and David Culler.
Queue Pair IP: A Hybrid Architecture for System Area Networks,
Symposium on Computer Architecture,
May 2002 (other:
pdf). **** NEW! ****
- L3:
Lionel M. Ni and Philip McKinley.
A Survey of Wormhole Routing Techniques in Direct Networks,
IEEE Computer,
February 1993, pp. 62-76
(B7).
Single Instruction Multiple Data (SIMD) and Future Trends
- Text: Skim Chapter 12
- L3:
D. J. Kuck and R. A. Stokes,
The Burroughs Scientific Processor (BSP),
IEEE Trans. on Computers,
May 1982, pp. 363-373
(B8).
- L3:
W. Daniel Hillis and Guy L. Steele,
Data Parallel Algorithms,
Communications of the ACM,
December 1986, pp. 1170-1183
(other: not online?).
- L3:
Charles E. Leiserson and others,
The Network Architecture of the Connection Machine CM-5,
The Journal of Parallel and Distributed Computing,
March 15, 1996 (revised from SPAA 1992)
(other: ps.Z).
- L3:
M. Gokhale, B. Holmes, and K. Iobst,
Processing in Memory: The Terasys Massively Parallel PIM Array,
IEEE Computer,
April 1995, pp. 23-31
(B8).
- L3:
Arvind and Rishiyur S. Nikhil,
Executing a Program on the MIT Tagged-Token Dataflow Architecture,
IEEE Trans. on Computers,
Mar 1990, pp. 300-318
(B5).
- L3:
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood,
SafetyNet: Improving the Availability of Shared Memory Multiprocessors
with Global Checkpoint/Recovery,
Symposium on Computer Architecture,
May 2002 (other:
pdf). **** NEW! ****