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CS/ECE 757: Advanced Computer Architecture II
Spring 2004 Section 1 of 1
Instructor Mark D. Hill and T. A. David Mulvihill
URL: http://www.cs.wisc.edu/~markhill/cs757/Spring2004/

Reading List for Exam 2

Last updated on Monday, 29-Mar-2004 14:32:10 CST

Chip Multiprocessors 1

Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Proc. 23rd Annual International Symposium on Computer Architecture, May 1996, pp. 191-202 (ps). UNREVIEW DUE: Fri Feb 20 (see email log for question to be answered)

Lance Hammond, Ben Hubbert, Michael Siu, Manohar Prabhu, Mike Chen, and Kunle Olukotun The Stanford Hydra CMP, IEEE Micro, March-April 2000, pp. 71-84. (pdf). UNREVIEW DUE: Fri Feb 20 (see email log for question to be answered)

Gurindar S. Sohi and Amir Roth, Speculative Multithreaded Processors, IEEE Computer, April 2001, pp. 66-73. (pdf). UNREVIEW DUE: Mon Feb 23 (see email log for question to be answered)

Distributed Shared Memory 1

James Laudon and Daniel Lenoski The SGI Origin: A ccNUMA Highly Scalable Server, In Proceedings of International Symposium on Computer Architecture, pages 241-251, June 1997 (pdf). UNREVIEW DUE: Wed Feb 25 (see email log for question to be answered)

Sarita V. Adve and Kourosh Gharachorloo, Shared Memory Consistency Models: A Tutorial, IEEE Computer, 29(12):66-76, December 1996 (pdf). UNREVIEW DUE: Fri Feb 27 (see email log for question to be answered)

Mark D. Hill, Multiprocessors Should Support Simple Memory Consistency Models, IEEE Computer, August 1998 (pdf). UNREVIEW DUE: Mon Mar 1 (see email log for question to be answered)

Milo M. K. Martin, Mark D. Hill, and David A. Wood, Token Coherence: Decoupling Performance and Correctness, International Symposium on Computer Architecture, June 2003 (pdf).

Chip Multiprocessors 2

J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, POWER4 system microarchitecture, IBM J. of Research and Development,, 2002, vol. 46, no. 1, pp 5., (html). UNREVIEW DUE: Wed Mar 3 (see email log for question to be answered)

Ron Kalla, Balaram Simharoy, and Joel Tendler, POWER5 Slides, Hot Chips,, 2003 (pdf). FOR YOUR INFORMATION

Luiz Andre Barroso, et al., Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing, Proc. International Symposium on Computer Architecture, June 2000, pp. 282-293 (pdf). UNREVIEW DUE: Wed Mar 3 (see email log for question to be answered)

Scalable Systems

Skim Chapter 7 of Text

Steven L. Scott, Synchronization and Communication in the T3E Multiprocessor, Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems, pages 26-36, October 1996 (pdf). UNREVIEW DUE: Mon Mar 8 (see email log for question to be answered)

Steve Scott, Cray X1 Slides, Wisconsin,, 2003 (pdf). FOR YOUR INFORMATION

Cristiana Amza, et al., TreadMarks: Shared Memory Computing on Networks of Workstation, IEEE Computer, 29(2):18-28, February 1996 (pdf). UNREVIEW DUE: Wed Mar 10 (see email log for question to be answered)

Erik Hagersten and Michael Koster, WildFire: A Scalable Path for SMPs, Proc. High-Performance Computer Architecture, January 1999 (pdf). UNREVIEW DUE: Fri Mar 12 (see email log for question to be answered)

Luiz Andre Barroso, Jeffrey Dean, Urs Holzle, Web Search For a Planet: The Google Cluster Architecture, IEEE Micro, 23(2):22-28, March-April 2003 ( pdf). NO UNREVIEW

Interconnection Networks

Chapter 10 of Text

Shubhendu S. Mukherjee, Peter Bannon, Steven Lang, Aaron Spink, and David Webb The Alpha 21364 Network Architecture, IEEE Micro, Janaury-Febraury 2002, pp. 45-54. (pdf). UNREVIEW DUE: Fri Mar 26 (see email log for question to be answered)

Single Instruction Multiple Data (SIMD) and Miscellanious

Charles E. Leiserson and others, The Network Architecture of the Connection Machine CM-5, The Journal of Parallel and Distributed Computing, March 15, 1996 (revised from SPAA 1992) (pdf). NO UNREVIEW

M. Gokhale, B. Holmes, and K. Iobst, Processing in Memory: The Terasys Massively Parallel PIM Array, IEEE Computer, April 1995, pp. 23-31 (pdf). NO UNREVIEW