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CS/ECE 757 Parallel Computer Architecture (Spring 2019)

Officially: Advanced Computer Architecture II (Section 1 of 1)
Instructor: Mark D. Hill; URL: http://www.cs.wisc.edu/~markhill
Meeting time: 1257 CS, 1:00 - 2:15 PM, MWF
Course URL: http://pages.cs.wisc.edu/~markhill/cs757/Spring2019/wiki/

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Motivation

''The distant threat has come to pass. For 30 years or more, pundits have claimed that parallel computers are the inexorable next step in the evolution of computers. --Jim Larus & Ravi Rajwar, Transactional Memory, Morgan & Claypool, Editor Mark Hill, 2007''

Multicore processors multiplying two ways: in market share and cores per chip. Mainstream vendors are shipping chips with 4, 6, and 8 cores, often with multithreading support. More aggressive chips target 48 to 336 non-traditional cores.

CS 757 will help you understand how multicore and other parallel systems work. We will mix some programming with detailed study of the hardware architectures.

Prerequisite CS/ECE 752 NOT Required

This offering of CS/ECE 757 will use CS/ECE 552 (or basic architecture knowledge) as its principal prerequisite. It does not require CS/ECE 752 (despite what the course catalog and timetable say). This is because our focus will be on parallelism issues, not details of core pipelines.

Instructions for First Lecture (Wed Jan 23, 2019)

If you want to get a big head start, check out: Introduction to Parallel Computing, Blaise Barney, Lawrence Livermore National Laboratory

Learning Outcomes

CS/ECE 757 qualitatively and quantitatively examines the fundamental computer architecture principles of parallel computer systems. (Click here to see Bloom's Taxonomy at end.) Course learning outcomes include:

  • Analyze pertinent research papers, including writing reviews of them.
  • Understand how semiconductor technology and information technology applications influence parallel computer systems.
  • Implement parallel computer programs in multiple paradigms (e.g., data parallel, shared-memory, and message-passing) and understand trade-offs among the paradigms.
  • Understand and evaluate different synchronization mechanisms, memory consistency models, cache coherence protocols
  • Understand and evaluate interconnection network goals and mechanisms.
  • Analyze and evaluate parallel computer systems by user and enhancing at least one simulator of such systems.
  • Understand and evaluate emerging heterogeneous parallelism design approaches, e.g., single instruction multiple data (SIMD), single instruction multiple thread (SIMT), and other accelerators.
  • Either (a) create a novel parallel computer architecture research idea and investigate evaluate its potential through the course project or (b) understand and analyze a sub-field of parallel computer systems by writing a capstone survey paper.

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