An Analysis of Cache Sharing in Chip Multiprocessors
by Brian Forney, Steve Hart, and Matt McCormick
We present the effects of L1 and L2 cache sharing on cache miss rates,
cache line invalidations, and constuctive and destructive interference.
The most important finding of this paper is that a system configuration
that shares L2 caches, does not share L1 caches, and does not enforce
inclusion between the L1 and L2 caches will produce the highest
performance cache and communication hierarchy for a chip multiprocessor.
This is due to the relatively high speed of communication through the
L2 cache but the low effects of L2 sharing on L1 performance - if
inclusion is not enforced. Sharing at the L1 level produces too many
conflict misses at this all important resource.
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