Hongil Yoon

Hongil Yoon

Current Position

Education

  • Ph.D. (May 2017) Computer Sciences, University of Wisconsin-Madison, Madison, WI
  • M.S. (May 2012) Computer Sciences, University of Wisconsin-Madison, Madison, WI
  • B.S. (Feb. 2007) Computer Sciences and Engineering, Korea University, Seoul, Republic of Korea

Research Information

Overview

  • I earned my PhD, with a focus in computer architecture, in May of 2017. I worked in Multiscalar Group, advised by Dr. Gurindar S. Sohi. I am interested in the area of cache mechanism, including coherence, consistency, a new cache organization, and interactions between hardware and operating systems.

    For my dissertation, I worked on a new virtual cache design to save the power/energy and latency overheads resulting from address translation.

    I am a staff silicon engineer at Google in Mountain View, CA.

Dissertation

  • Reducing Address Translation Overheads with Virtual Caching. Dissertation, March 2017.
    Dissertation: pdf
    Defense Talk: pptx

Publications

  • Sam Son, Seung Yul Lee, Yunho Jin, and Jonghyun Bae, Seoul National University; Jinkyu Jeong, Sungkyunkwan University; Tae Jun Ham and Jae W. Lee, Seoul National University; Hongil Yoon, Google
    ASAP: Fast Mobile Application Switch via Adaptive Prepaging
    2021 USENIX Annual Technical Conference
    Paper: Local Copy
  • The gem5 Simulator: Version 20.0+
    arXiv:2007.03152, July, 2020
    Paper: arXiv
  • Hongil Yoon, Jason Lowe-Power, and Gurindar S. Sohi.
    Filtering Translation Bandwidth with Virtual Caching.
    The 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2018), March 2018.
    Paper: Local Copy, DOI (ACM DL)
  • Vijay Janapa Reddi, Hongil Yoon, and Allan Knies.
    Two Billion Devices and Counting: An Industry Perspective on the State of Mobile Computer Architecture.
    IEEE MICRO - Expert Opinion, February 2018.
    Paper: Local Copy, DOI (IEEE Xplore)
  • Hongil Yoon and Gurindar S. Sohi.
    Revisiting Virtual L1 Caches: A Practical Design Using Dynamic Synonym Remapping.
    The 22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA-22), March 2016.
    Paper: DOI (IEEE Xplore)

Patents

  • System-Level Cache [Link]
  • Gurindar S. Sohi and Hongil Yoon
    Cache Accessed Using Virtual Addresses. US20160188486A1 [Link]
  • Gurindar S. Sohi and Hongil Yoon
    Computer Cache System Providing Multi-Line Invalidation Messages. U.S. Patent No. 9,223,717 [Link]

Tech Report

  • Hongil Yoon, Jason Lowe-Power, and Gurindar S. Sohi.
    Reducing GPU Address Translation Overhead with Virtual Caching.
    Tech Report TR-1842, Computer Sciences Department, University of Wisconsin-Madison, December 2016. [Link]
  • Hongil Yoon and Gurindar S. Sohi.
    Revisiting Virtual L1 Caches: A Practical Design Using Dynamic Synonym Remapping.
    Tech Report TR-1826, Computer Sciences Department, University of Wisconsin-Madison, October 2015. [Link]
  • Hongil Yoon and Gurindar S. Sohi.
    Region-level Tracking for Scalable Directory Cache.
    Tech Report TR-1823, Computer Sciences Department, University of Wisconsin-Madison, April 2015. [Link]
  • Hongil Yoon and Gurindar S. Sohi.
    Reducing Coherence Overheads with Multi-line Invalidation (MLI) Messages.
    Tech Report TR-1816, Computer Sciences Department, University of Wisconsin-Madison, May 2013. [Link]
  • Hongil Yoon, Tan Zhang, and Mikko H. Lipasti.
    SIP: Speculative Insertion Policy for High Performance Caching.
    Tech Report TR-1676, Computer Sciences Department, University of Wisconsin-Madison, 2010. [Link]

Updated November 4, 2020. William C. Benton's CSS file is used for this web page.