Harish G. Patil

Education:

Research Interests:

Research Summary:

• Researched ways to reduce execution-time overhead of program monitoring.
  
• Proposed and investigated two techniques for speeding up monitoring.
  
  1. Using idle processors in multi-processor workstations.
  2. Using executable program slices.
• Built a memory access checking system for C programs.
  
• Developed a prototype slicing tool for C programs. [Based on a slicing back end from the Wisconsin Program Slicing project.]
  

• Investigated ways to handle the solution complexity of bi-directional data-flow problems.
  
• Developed an elimination algorithm for bi-directional data flow problems using edge-placement.
  

Ph.D. Dissertation:

Efficient Program Monitoring Techniques Harish G. Patil, Ph.D. Dissertation.

Available as technical report CS-TR-96-1320.

M.Tech. Thesis:

Studies in Bi-directional Data Flow Analysis Harish G. Patil, Master's Thesis, Department of Computer Science and Engineering, Indian Institute of Technology, Bombay, 1989.

Patents:

Unwind information for optimized programs. Patil; Harish G., Muth; Robert, Lowney; Geoff. Intel Corporation. United States Patent 7,480,902 , granted January 20, 2009.

Branch prediction combining static and dynamic prediction techniques. Patil; Harish G., Emer; Joel S., Felix; Stephen. Hewlett-Packard Development Company. (Research done at Compaq.) United States Patent 7,404,070 , granted July 22, 2008.

Method and apparatus for debugging of optimized code using emulation. Mirani; Rajiv, Olsen; Bruce A., Patil; Harish G. Hewlett-Packard Company. United States Patent 6,434,741 , granted August 13, 2002.

Publications:

PinPlay: A Framework for Deterministic Replay and Reproducible Analysis of Parallel Programs. Harish Patil, Cristiano Pereira, Mack Stallcup, Gregory Lueck, and James Cownie. In proceedings of International Symposium on Code Generation and Optimization (CGO), April 2010.

Reproducible Simulation of Multi-Threaded Workloads for Architecture Design Exploration. Cristiano Pereira, Harish Patil, and Brad Calder In proceedings of International Symposium on Workload Characterization (IISWC'08), Sept 2008.

Cross Binary Simulation Points. Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jaleel, Greg Hamerly, and Brad Calder. In proceedings of International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2007.

Automatic Logging of Operating System Effects to Guide Application-Level Architecture Simulation Satish Narayanasamy, Cristiano Pereira, Harish Patil, Robert Cohn, and Brad Calder In proceedings of ACM SIGMETRICS the International Conference on Measurement and Modeling of Computer Systems, June 2006. Full paper in PDF.

Pin: building customized program analysis tools with dynamic instrumentation. Luk, C., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Vijay Janapa Reddi, and Hazelwood, K. In Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation (Chicago, IL, USA, June 12 - 15, 2005).

Pinpointing Representative Portions of Large Intel Itanium Programs with Dynamic Instrumentation. Harish Patil, Robert Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, and Anand Karunanidhi. In proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-37), December, 2004. Full paper in PDF.

Ispike: A Post-link Optimizer for the IntelŽItaniumŽArchitecture Chi-Keung Luk, Robert Muth, Harish Patil, Robert Cohn, Geoff Lowney. In proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, 2004.

Asim: A Performance Model Framework. Joel Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan Binkert, Roger Espasa, and Toni Juan. In IEEE Computer, February 2002.

Kernel Optimizations and Prefetch with the Spike Executable Optimizer Richard Flower, Chi-Keung Luk, Robert Muth, Harish Patil, John Shakshober, Robert Cohn, and P. Geoffrey Lowney Appears in the proceedings of 4th Workshop on Feedback-Directed and Dynamic Optimization (FDDO-4), December 2001 . Full paper in PDF.

Combining Static and Dynamic Branch Prediction to Reduce Desctructive Aliasing [abstract] Harish Patil and Joel Emer (Alpha Development Group, Compaq Computer Corporation) Appears in the proceedings of HPCA-6, January, 2000. Full paper in PDF.

A New Framework For Debugging Globally Optimized Code Le-Chun Wu (UIUC), Rajiv Mirani(HP), Harish Patil(HP), Bruce Olsen(HP), and Wein-Mei Hwu(UIUC). Appears in the proceedings of PLDI'99. Postscript

Low-cost, Concurrent Checking of Pointer and Array Accesses in C programs Harish Patil and Charles Fischer. Software - Practice and Experience, pages 87-110, Volume 27,Number 1, January, 1997. Postscript

Efficient Run-time Monitoring Using Shadow Processing Harish Patil and Charles Fischer, Presented at AADEBUG'95, St. Malo, France, May 1995.
More on our AADEBUG'95 presentation

Shadow Guarding: Run-time Checking You Can Afford Harish Patil and Charles Fischer, Technical Report Number 1254, Computer Sciences Department, UW-Madison, November 1994.
Original technical report.
A thoroughly updated and extended version: appeared in Software - Practice & Experience

An Elimination Algorithm for Bi-directional Data Flow Problems Using Edge Placement D. M. Dhamdhere and Harish Patil, ACM TOPLAS, Vol. 15, No. 2, April 1993

Miscellaneous: