My research focuses on automatic construction of software assist threads to exploit new trendy single-chip parallel processors which efficiently support small-scale closely-coupled concurrency. These processors use flavors of simultaneous multi-threading (SMT) and chip-multiprocessing (CMP) (and combinations thereof), and include the Intel Pentium 4, IBM Power4 and Power5, Sun UltraSPARC IV and V, and quite probably all future general-purpose microprocessors. I look for coarse-grained parallelism in the "support" code generated by compilers of high-level languages such as Java. Which means that, rather than parallelizing arbitrary application code itself, I offload easily recognizable auxiliary tasks such as profiling, monitoring, memory management and other dynamic analyses to assist threads. The final "product" of my research is a general framework with analysis and transformation techniques, guided by a cost model, to generate such threads in a Java compiler.


In past lives, I have also worked with research groups that have tackled verification of memory consistency models, and that have designed new coherence protocols for modern shared-memory multiprocessors.


I've also spent a rather unhealthy amount of my incarceration in graduate school deep in the bowels of multiple simulators, compiler backends and language runtimes. Analyzing benchmarks. Dreaming up optimizations. Obsessing with low-level performance improvement. Which is rarely found cleanly. Or without inordinate effort. Given Moore's Law and Proebsting's Law, I now have some respect for the the long-term relevancy and cost-effectiveness of software research in functionality, productivity, correctness and reliability, rather than (compiler-orchestrated) performance. And a view of entire systems, rather than a blinkered view of components we are most interested in, and which might not be that important in the big picture. See Arch Robinson's keynote for an industry perspective on compiler optimization.

Updated on 15 Feb 2004