*** alpha.h.orig	Fri Apr  2 16:58:30 1999
--- alpha.h	Sat Feb 27 10:17:16 1999
***************
*** 129,134 ****
--- 129,136 ----
    md_fault_alignment,		/* storage alignment fault */
    md_fault_overflow,		/* signed arithmetic overflow fault */
    md_fault_div0,		/* division by zero fault */
+   md_fault_invalid,             /* invalid arithmetic operation */ 
+                                 /* -- Added to allow SQRT{S,T} in FIX extensions */
    md_fault_break,		/* BREAK instruction fault */
    md_fault_unimpl,		/* unimplemented instruction fault */
    md_fault_internal		/* internal S/W fault */
***************
*** 158,164 ****
  /* floating point register file entry type */
  typedef union {
    quad_t q[MD_NUM_FREGS];	/* integer quad view */
!   dfloat_t d[MD_NUM_FREGS];	/* double-prediction floating point view */
  } md_fpr_t;
  
  /* control register file contents */
--- 160,166 ----
  /* floating point register file entry type */
  typedef union {
    quad_t q[MD_NUM_FREGS];	/* integer quad view */
!   dfloat_t d[MD_NUM_FREGS];	/* double-precision floating point view */
  } md_fpr_t;
  
  /* control register file contents */
***************
*** 218,224 ****
  
  /* largest opcode field value (currently upper 8-bit are used for pre/post-
      incr/decr operation specifiers */
! #define MD_MAX_MASK		1024
  
  /* internal decoder state */
  extern enum md_opcode md_mask2op[];
--- 220,228 ----
  
  /* largest opcode field value (currently upper 8-bit are used for pre/post-
      incr/decr operation specifiers */
! #define MD_MAX_MASK		2048  /* -- Increased from 1024 to 
! 				       * -- accomodate new instructions in alpha.def 
! 				       */
  
  /* internal decoder state */
  extern enum md_opcode md_mask2op[];
***************
*** 320,325 ****
--- 324,335 ----
  
  /* test for arithmetic overflow */
  #define ARITH_OVFL(RESULT, OP1, OP2) ((RESULT) < (OP1) || (RESULT) < (OP2))
+ 
+ /* -- test for NaN */
+ #define IEEEFP_DBL_SIGN(Q)      ((Q) >> 63)
+ #define IEEEFP_DBL_EXPONENT(Q)  (((Q) >> 52) & 0x7ff)
+ #define IEEEFP_DBL_FRACTION(Q)  ((Q) & ULL(0xfffffffffffff))
+ #define IS_IEEEFP_DBL_NAN(Q)    ( ( IEEEFP_DBL_EXPONENT(Q) == 0x7ff) && ( IEEEFP_DBL_FRACTION(Q)) )
  
  /* default target PC handling */
  #ifndef SET_TPC