Summary of changes: All these fixes were verified by running `make sim-tests' in the top-level simplescalar-3.0a directory. Additionally, I've also tested some of the fixes using optimized SPECint95 binaries. 
The `make sim-tests' regression tests worked fine.
I generated optimized SPECINT95 binaries on the EV56 box
here using `cc.alt -arch ev56 -non_shared -O4' and all of them
ran fine using sim-safe. Sim-outorder runs also completed.
I haven't tried SPECFP95 (mainly 'cos the machine doesn't have 
a native Fortran compiler installed and I haven't got around to 
compiling f2c for Alpha).

My EV56 binaries pretty much needed only the AMASK instruction since BWX
(load-store byte/word) support was already there in alpha-bwx.def provided
by Todd. I tested the EV6 extensions using hand-coded assembly: the native 
assembler understood these instructions and they were emulated by the OS 
(I did not have access to an EV6 box at the time). Sim-safe's output matched 
that of the native Alpha. It would be great to get some binaries that 
actually make heavy use of these instructions, for testing purposes.

I have not added any PALcode instructions and have not done any
testing of the existing instruction definitions.

 - Added:  (40 instructions)
           ([xxxx] refers to the instruction group name in the Alpha manual)
     - [INTL] AMASK, IMPLVER
     - [MISC] EXCB, WMB, RC, ECB, WH64
     - [ITFP] (FIX extensions) ITOF{S,T},SQRT{S,T}
	      (and added unimplemented entries for ITOFF,SQRT{F,G})
     - [FPTI] (FIX extensions) FTOI{S,T}
	      (CIX extensions) CTPOP, CT{L,T}Z
	      (MVI extensions) PERR, PK{W,L}B,UNPKB{W,L},{MIN,MAX}{U,S}{B8,W4}

 - Implemented: (7 instructions)
     - FETCH, FETCH_M, RPCC, RS (=>NOPs)
     - CMPTUN 
     - MUL{Q,L}/V (changed INTM's mask to map MUL{Q,L}/V to MUL{Q,L})

 - Fixed:
     - [alpha.h] Changed MD_MAX_MASK from 1024 to 2048 
     - [alpha.h] Added md_fault_invalid for SQRT(-ve) traps
     - [alpha.h] Added macro to test for IEEE FP NaN (for CMPTUN)


 - Final status:
     - ALL EV6 ISA instructions have entries in alpha-ev6.def 
	  (including all extensions: BWX, FIX, CIX, MVI)

     - The following instructions generate md_fault_unimpl faults:
	- VAX FP loads/stores
        - All VAX FP operate instructions 

     - The following instructions are NOPs:
	- [barriers] TRAPB, EXCB, MB, WMB
	- [cache hints] FETCH, FETCH_M, ECB, WH64
	- [misc] RPCC, RC, RS

     - Instruction qualifiers (trap+rounding) are currently ignored, and the 
       FPCR is not read/written by any FP instruction (apart from M{T,F}_FPCR)

     - Some single-precision FP operations execute using double-precision

     - LD{L,Q}_L and ST{L,Q}_C are not fully implemented



Rajeev Balasubramonian (rajeev@cs.rochester.edu) had some problems running a 
SPECint95 vortex binary generated on an Alpha 21164 machine. The problem was
traced to not implementing two OSF/1 system calls: syscall() and table().
Cases were added to syscall.c to handle these two system calls. I also made
some changes to allow the file to be compiled on an Alpha/OSF box. 

I changed the default case so that unimplemented system calls would 
simply appear to fail to the simulated program (instead of aborting
the simulation). An informative message (with system call number and
PC) is printed out. 

No-op cases for mkdir() and shmget() calls were added to enable GLQuake
to run on Simplescalar.

This file is based on an updated SS-Alpha distribution that had been made 
available to some Solaris/x86 users (not part of the initial SS-3.0a 
pre-release) and hence it might look a little different from what you 
currently have.

Carlos Navarro (cnavarro@ac.upc.es) and Alex Ramirez (aramirez@ac.upc.es) had 
problems running some Alpha binaries which were traced to conditional branches 
using a 16-bit offset from the instruction rather than a 21-bit offset as 
specified in the Alpha ISA.  Todd Austin (taustin@eecs.umich.edu) provided a fix 
for this bug.
[note]Last updated on Feb 29 1996