*** alpha-orig.def Wed Nov 3 18:53:39 1999 --- alpha-latest.def Wed Nov 3 18:46:31 1999 *************** *** 229,234 **** --- 229,251 ---- IntALU, F_ICOMP, DGPR(RA), DNA, DNA, DGPR(RB), DNA) + /* EV56 BWX extension... */ + #define LDBU_IMPL \ + { \ + byte_t _result; \ + enum md_fault_type _fault; \ + \ + _result = READ_BYTE(GPR(RB) + SEXT(OFS), _fault); \ + if (_fault != md_fault_none) \ + DECLARE_FAULT(_fault); \ + \ + SET_GPR(RA, (quad_t)_result); \ + } + DEFINST(LDBU, 0x0a, + "ldbu", "a,o(b)", + RdPort, F_MEM|F_LOAD|F_DISP, + DGPR(RA), DNA, DNA, DGPR(RB), DNA) + #define LDQ_U_IMPL \ { \ quad_t _result; \ *************** *** 245,250 **** --- 262,312 ---- RdPort, F_MEM|F_LOAD|F_DISP, DGPR(RA), DNA, DNA, DGPR(RB), DNA) + /* EV56 BWX extension... */ + #define LDWU_IMPL \ + { \ + half_t _result; \ + enum md_fault_type _fault; \ + \ + _result = READ_HALF(GPR(RB) + SEXT(OFS), _fault); \ + if (_fault != md_fault_none) \ + DECLARE_FAULT(_fault); \ + \ + SET_GPR(RA, (quad_t)_result); \ + } + DEFINST(LDWU, 0x0c, + "ldwu", "a,o(b)", + RdPort, F_MEM|F_LOAD|F_DISP, + DGPR(RA), DNA, DNA, DGPR(RB), DNA) + + /* EV56 BWX extension... */ + #define STW_IMPL \ + { \ + enum md_fault_type _fault; \ + \ + WRITE_HALF((half_t)GPR(RA), GPR(RB) + SEXT(OFS), _fault); \ + if (_fault != md_fault_none) \ + DECLARE_FAULT(_fault); \ + } + DEFINST(STW, 0x0d, + "stw", "a,o(b)", + WrPort, F_MEM|F_STORE|F_DISP, + DNA, DNA, DGPR(RA), DGPR(RB), DNA) + + /* EV56 BWX extension... */ + #define STB_IMPL \ + { \ + enum md_fault_type _fault; \ + \ + WRITE_BYTE((byte_t)GPR(RA), GPR(RB) + SEXT(OFS), _fault); \ + if (_fault != md_fault_none) \ + DECLARE_FAULT(_fault); \ + } + DEFINST(STB, 0x0e, + "stb", "a,o(b)", + WrPort, F_MEM|F_STORE|F_DISP, + DNA, DNA, DGPR(RA), DGPR(RB), DNA) + #define STQ_U_IMPL \ { \ enum md_fault_type _fault; \ *************** *** 264,270 **** DEFLINK(INTS, 0x12, "ints", 5, 0x7f) ! DEFLINK(INTM, 0x13, "intm", 5, 0x7f) #define FLTV_IMPL \ { \ --- 326,340 ---- DEFLINK(INTS, 0x12, "ints", 5, 0x7f) ! DEFLINK(INTM, 0x13, "intm", 5, 0x3f) /* -- Changed from 0x7f to 0x3f to allow MUL{Q,L}/V */ ! ! /* ! * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) ! */ ! ! /* -- FIX extensions */ ! DEFLINK(ITFP, 0x14, "itfp", 5, 0x3f ) ! #define FLTV_IMPL \ { \ *************** *** 280,289 **** DEFLINK(FLTL, 0x17, "fltl", 5, /* FIXME: check this... */0x7f) ! DEFLINK(MISC, 0x18, "misc", 12, 0x0f) DEFLINK(JMPJSR, 0x1a, "jmpjsr", 14, 0x03) #define LDF_IMPL \ { \ /* FIXME: unimplemented */ \ --- 350,363 ---- DEFLINK(FLTL, 0x17, "fltl", 5, /* FIXME: check this... */0x7f) ! /* -- Changed the shift & mask to incorporate new instructions in the group */ ! DEFLINK(MISC, 0x18, "misc", 8, 0xff) DEFLINK(JMPJSR, 0x1a, "jmpjsr", 14, 0x03) + /* -- Changed from EXTS to FPTI to include more extensions (FIX,CIX,MVI) */ + DEFLINK(FPTI, 0x1c, "fpti", 5, 0x7f) + #define LDF_IMPL \ { \ /* FIXME: unimplemented */ \ *************** *** 541,549 **** #define FBEQ_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (FPR(RA) == 0.0) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(FBEQ, 0x31, "fbeq", "A,j", --- 615,623 ---- #define FBEQ_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (FPR(RA) == 0.0) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(FBEQ, 0x31, "fbeq", "A,j", *************** *** 552,560 **** #define FBLT_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (FPR(RA) < 0.0) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(FBLT, 0x32, "fblt", "A,j", --- 626,634 ---- #define FBLT_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (FPR(RA) < 0.0) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(FBLT, 0x32, "fblt", "A,j", *************** *** 563,571 **** #define FBLE_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (FPR(RA) <= 0.0) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(FBLE, 0x33, "fble", "A,j", --- 637,645 ---- #define FBLE_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (FPR(RA) <= 0.0) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(FBLE, 0x33, "fble", "A,j", *************** *** 587,595 **** #define FBNE_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (FPR(RA) != 0.0) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(FBNE, 0x35, "fbne", "A,j", --- 661,669 ---- #define FBNE_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (FPR(RA) != 0.0) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(FBNE, 0x35, "fbne", "A,j", *************** *** 598,606 **** #define FBGE_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (FPR(RA) >= 0.0) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(FBGE, 0x36, "fbge", "A,j", --- 672,680 ---- #define FBGE_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (FPR(RA) >= 0.0) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(FBGE, 0x36, "fbge", "A,j", *************** *** 609,617 **** #define FBGT_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (FPR(RA) > 0.0) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(FBGT, 0x37, "fbgt", "A,j", --- 683,691 ---- #define FBGT_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (FPR(RA) > 0.0) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(FBGT, 0x37, "fbgt", "A,j", *************** *** 620,628 **** #define BLBC_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (!(GPR(RA) & 1)) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(BLBC, 0x38, "blbc", "a,j", --- 694,702 ---- #define BLBC_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (!(GPR(RA) & 1)) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(BLBC, 0x38, "blbc", "a,j", *************** *** 631,639 **** #define BEQ_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (GPR(RA) == ULL(0)) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(BEQ, 0x39, "beq", "a,j", --- 705,713 ---- #define BEQ_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (GPR(RA) == ULL(0)) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(BEQ, 0x39, "beq", "a,j", *************** *** 642,650 **** #define BLT_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if ((squad_t)GPR(RA) < LL(0)) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(BLT, 0x3a, "blt", "a,j", --- 716,724 ---- #define BLT_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if ((squad_t)GPR(RA) < LL(0)) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(BLT, 0x3a, "blt", "a,j", *************** *** 653,661 **** #define BLE_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if ((squad_t)GPR(RA) <= LL(0)) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(BLE, 0x3b, "ble", "a,j", --- 727,735 ---- #define BLE_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if ((squad_t)GPR(RA) <= LL(0)) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(BLE, 0x3b, "ble", "a,j", *************** *** 664,672 **** #define BLBS_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (GPR(RA) & 1) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(BLBS, 0x3c, "blbs", "a,j", --- 738,746 ---- #define BLBS_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (GPR(RA) & 1) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(BLBS, 0x3c, "blbs", "a,j", *************** *** 675,683 **** #define BNE_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if (GPR(RA) != ULL(0)) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(BNE, 0x3d, "bne", "a,j", --- 749,757 ---- #define BNE_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if (GPR(RA) != ULL(0)) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(BNE, 0x3d, "bne", "a,j", *************** *** 686,694 **** #define BGE_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if ((squad_t)GPR(RA) >= LL(0)) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(BGE, 0x3e, "bge", "a,j", --- 760,768 ---- #define BGE_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if ((squad_t)GPR(RA) >= LL(0)) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(BGE, 0x3e, "bge", "a,j", *************** *** 697,705 **** #define BGT_IMPL \ { \ ! SET_TPC(CPC + (SEXT(OFS) << 2) + 4); \ if ((squad_t)GPR(RA) > LL(0)) \ ! SET_NPC(CPC + (SEXT(OFS) << 2) + 4); \ } DEFINST(BGT, 0x3f, "bgt", "a,j", --- 771,779 ---- #define BGT_IMPL \ { \ ! SET_TPC(CPC + (SEXT21(TARG) << 2) + 4); \ if ((squad_t)GPR(RA) > LL(0)) \ ! SET_NPC(CPC + (SEXT21(TARG) << 2) + 4); \ } DEFINST(BGT, 0x3f, "bgt", "a,j", *************** *** 1305,1314 **** --- 1379,1413 ---- DEFLINK(EQV_LINK, 0x48, "eqv_link", 12, 1) + /* + * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) + */ + + DEFLINK(AMASK_LINK, 0x61, "amask_link", 12, 1) + DEFLINK(CMOVLE_LINK, 0x64, "cmovle_link", 12, 1) DEFLINK(CMOVGT_LINK, 0x66, "cmovgt_link", 12, 1) + /* + * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) + */ + + /* + * -- Major implementation version of processor, used for code-scheduling + * -- decisions, rather than ISA decisions. Makes sense to return EV6 + * -- for sim-outorder. + */ + #define IMPLVER_IMPL \ + { \ + SET_GPR(RC, ULL(2)); \ + } + DEFINST(IMPLVER, 0x6c, + "implver", "c", + NA, NA, + DGPR(RC), DNA, DNA, DNA, DNA) + + CONNECT(AND_LINK) *************** *** 1573,1578 **** --- 1672,1709 ---- IntALU, F_ICOMP|F_IMM, DGPR(RC), DNA, DGPR(RA), DNA, DNA) + + /* + * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) + */ + CONNECT(AMASK_LINK) + + /* + * -- AMASK queries support for ISA extensions, currently we support: + * -- - BWX (clear bit 0) + * -- - FIX (clear bit 1) + * -- - CIX (clear bit 2) + * -- - MVI (clear bit 8) + */ + + #define AMASK_IMPL \ + { \ + SET_GPR(RC, GPR(RB) & ULL(0xfffffffffffffef8) ); \ + } + DEFINST(AMASK, 0x00, + "amask", "b,c", + NA, NA, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + #define AMASKI_IMPL \ + { \ + SET_GPR(RC, IMM & ULL(0xfffffffffffffef8) ); \ + } + DEFINST(AMASKI, 0x01, + "amask", "i,c", + NA, F_IMM, + DGPR(RC), DNA, DNA, DNA, DNA) + CONNECT(CMOVLE_LINK) *************** *** 2290,2321 **** CONNECT(INTM) DEFLINK(MULL_LINK, 0x00, "mull_link", 12, 1) DEFLINK(MULQ_LINK, 0x20, "mulq_link", 12, 1) DEFLINK(UMULH_LINK, 0x30, "umulh_link", 12, 1) - #define MULLV_IMPL \ - { \ - /* FIXME: unimplemented */ \ - DECLARE_FAULT(md_fault_unimpl); \ - } - DEFINST(MULLV, 0x40, - "mull/v (unimpl)", "", - NA, NA, - DNA, DNA, DNA, DNA, DNA) - - #define MULQV_IMPL \ - { \ - /* FIXME: unimplemented */ \ - DECLARE_FAULT(md_fault_unimpl); \ - } - DEFINST(MULQV, 0x60, - "mulq/v (unimpl)", "", - NA, NA, - DNA, DNA, DNA, DNA, DNA) - CONNECT(MULL_LINK) --- 2421,2439 ---- CONNECT(INTM) + /* + * -- FIXME: + * -- Changed mask in DEFLINK(INTM ... above so that MUL{Q,L}/V now map + * -- to MUL{Q,L}, i.e. no overflow checking (earlier they generated + * -- unimplemented-faults). I think this is more symmetrical because + * -- {ADD,SUB}{L,Q}/V also do not check for overflow. + */ DEFLINK(MULL_LINK, 0x00, "mull_link", 12, 1) DEFLINK(MULQ_LINK, 0x20, "mulq_link", 12, 1) DEFLINK(UMULH_LINK, 0x30, "umulh_link", 12, 1) CONNECT(MULL_LINK) *************** *** 2433,2438 **** --- 2551,2663 ---- IntMULT, F_ICOMP|F_IMM, DGPR(RC), DNA, DGPR(RA), DNA, DNA) + /* + * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) + */ + + /* -- FIX extensions */ + CONNECT(ITFP) + + #define ITOFS_IMPL \ + { \ + squad_t _longhold, _e1, _e2; \ + \ + _longhold = GPR(RA) & ULL(0xffffffff); \ + \ + _e1 = _longhold & 0x40000000; \ + _e2 = (_longhold >> 23) & ULL(0x7f); \ + if (_e1) \ + { \ + if (_e2 == ULL(0x3f800000)) \ + _e2 = ULL(0x7ff); \ + else \ + _e2 |= ULL(0x400); \ + } \ + else \ + { \ + if (_e2 == 0) \ + _e2 = 0; \ + else \ + _e2 |= ULL(0x380); \ + } \ + SET_FPR_Q(RC, (((_longhold & ULL(0x80000000)) << 32) \ + | (_e2 << 52) | ((_longhold & ULL(0x7fffff)) << 29))); \ + } + DEFINST(ITOFS, 0x04, + "itofs", "a,C", + FloatCVT, F_FCOMP, /* -- FIXME: are these flags correct? */ + DFPR(RC), DNA, DGPR(RA), DNA, DNA) + + + #define SQRTF_IMPL \ + { \ + /* FIXME: unimplemented */ \ + DECLARE_FAULT(md_fault_unimpl); \ + } + DEFINST(SQRTF, 0x0a, + "sqrtf (unimpl)", "B,C", + NA, NA, + DNA, DNA, DNA, DNA, DNA) + + + #define SQRTS_IMPL \ + { \ + if( FPR(RB) < 0.0 ) \ + DECLARE_FAULT( md_fault_invalid ); \ + \ + /* -- FIXME: too much precision here */ \ + SET_FPR(RC, (dfloat_t) sqrt( (double) FPR(RB)) ); \ + } + DEFINST(SQRTS, 0x0b, + "sqrts", "B,C", + FloatSQRT, F_FCOMP, + DFPR(RC), DNA, DFPR(RB), DNA, DNA) + + + #define ITOFF_IMPL \ + { \ + /* FIXME: unimplemented */ \ + DECLARE_FAULT(md_fault_unimpl); \ + } + DEFINST(ITOFF, 0x14, + "itoff (unimpl)", "a,C", + NA, NA, + DNA, DNA, DNA, DNA, DNA) + + #define ITOFT_IMPL \ + { \ + SET_FPR_Q(RC, GPR(RA)); \ + } + DEFINST(ITOFT, 0x24, + "itoft", "a,C", + FloatCVT, F_FCOMP, /* -- FIXME: are these flags correct? */ + DFPR(RC), DNA, DGPR(RA), DNA, DNA) + + + #define SQRTG_IMPL \ + { \ + /* FIXME: unimplemented */ \ + DECLARE_FAULT(md_fault_unimpl); \ + } + DEFINST(SQRTG, 0x2a, + "sqrtg (unimpl)", "B,C", + NA, NA, + DNA, DNA, DNA, DNA, DNA) + + + #define SQRTT_IMPL \ + { \ + if( FPR(RB) < 0.0 ) \ + DECLARE_FAULT( md_fault_invalid ); \ + \ + SET_FPR(RC, (dfloat_t) sqrt( (double) FPR(RB)) ); \ + } + DEFINST(SQRTT, 0x2b, + "sqrtt", "B,C", + NA, NA, + DNA, DNA, DNA, DNA, DNA) + + CONNECT(FLTI) *************** *** 2518,2532 **** FloatDIV, F_FCOMP, DFPR(RC), DNA, DFPR(RA), DFPR(RB), DNA) ! #define CMPTUN_IMPL \ ! { \ ! /* FIXME: unimplemented */ \ ! DECLARE_FAULT(md_fault_unimpl); \ } DEFINST(CMPTUN, 0x24, ! "cmptun (unimpl)", "", ! NA, NA, ! DNA, DNA, DNA, DNA, DNA) #define CMPTEQ_IMPL \ { \ --- 2743,2758 ---- FloatDIV, F_FCOMP, DFPR(RC), DNA, DFPR(RA), DFPR(RB), DNA) ! #define CMPTUN_IMPL \ ! { \ ! SET_FPR( RC, (IS_IEEEFP_DBL_NAN( FPR_Q(RA) ) || IS_IEEEFP_DBL_NAN( FPR_Q(RB) )) \ ! ? 2.0 \ ! : 0.0 ); \ } DEFINST(CMPTUN, 0x24, ! "cmptun", "A,B,C", ! FloatCMP, F_FCOMP, ! DFPR(RC), DNA, DFPR(RA), DFPR(RB), DNA) #define CMPTEQ_IMPL \ { \ *************** *** 2644,2653 **** FloatADD, F_FCOMP, DFPR(RC), DNA, DFPR(RA), DFPR(RB), DNA) ! #define MT_FPCR_IMPL \ ! { \ ! /* FIXME: this looks incorrect, but what betadyn does... */ \ ! SET_FPCR(FPR(RA)); \ } DEFINST(MT_FPCR, 0x24, "mt_fpcr", "A", --- 2870,2880 ---- FloatADD, F_FCOMP, DFPR(RC), DNA, DFPR(RA), DFPR(RB), DNA) ! #define MT_FPCR_IMPL \ ! { \ ! /* FIXME: this looks incorrect, but what betadyn does... */ \ ! /* -- FIXED, 02/26/99, plakal@cecil, using Glew's fix, read FP reg as quad */ \ ! SET_FPCR(FPR_Q(RA)); \ } DEFINST(MT_FPCR, 0x24, "mt_fpcr", "A", *************** *** 2655,2671 **** DFPCR, DNA, DFPR(RA), DNA, DNA) #ifdef _MSC_VER ! #define MF_FPCR_IMPL \ ! { \ ! /* FIXME: quad_t to double conversion not implemented in MSC */ \ ! /* FIXME: this looks incorrect, but what betadyn does... */ \ ! SET_FPR(RA, (squad_t)FPCR); \ } #else /* !_MSC_VER */ ! #define MF_FPCR_IMPL \ ! { \ ! /* FIXME: this looks incorrect, but what betadyn does... */ \ ! SET_FPR(RA, FPCR); \ } #endif /* _MSC_VER */ DEFINST(MF_FPCR, 0x25, --- 2882,2900 ---- DFPCR, DNA, DFPR(RA), DNA, DNA) #ifdef _MSC_VER ! #define MF_FPCR_IMPL \ ! { \ ! /* FIXME: quad_t to double conversion not implemented in MSC */ \ ! /* FIXME: this looks incorrect, but what betadyn does... */ \ ! /* -- FIXED, 02/26/99, plakal@cecil, using Glew's fix, set FP reg as quad */ \ ! SET_FPR_Q(RA, FPCR); \ } #else /* !_MSC_VER */ ! #define MF_FPCR_IMPL \ ! { \ ! /* FIXME: this looks incorrect, but what betadyn does... */ \ ! /* -- FIXED, 02/26/99, plakal@cecil, using Glew's fix, set FP reg as quad */ \ ! SET_FPR_Q(RA, FPCR); \ } #endif /* _MSC_VER */ DEFINST(MF_FPCR, 0x25, *************** *** 2749,2754 **** --- 2978,2988 ---- CONNECT(MISC) + /* + * -- Note: some DEFINSTs below have different MSK values because the + * -- mask & shifts in the MISC link above have changed + */ + #define TRAPB_IMPL \ { \ /* FIXME: nada... */ \ *************** *** 2758,2813 **** NA, F_TRAP, DNA, DNA, DNA, DNA, DNA) #define MB_IMPL \ { \ /* FIXME: not supported... */ \ } ! DEFINST(MB, 0x04, "mb", "", NA, F_TRAP, DNA, DNA, DNA, DNA, DNA) #define FETCH_IMPL \ { \ ! /* FIXME: unimplemented */ \ ! DECLARE_FAULT(md_fault_unimpl); \ } ! DEFINST(FETCH, 0x08, ! "fetch (unimpl)", "", NA, NA, DNA, DNA, DNA, DNA, DNA) #define FETCH_M_IMPL \ { \ ! /* FIXME: unimplemented */ \ ! DECLARE_FAULT(md_fault_unimpl); \ } ! DEFINST(FETCH_M, 0x0a, ! "fetch_m (unimpl)", "", NA, NA, DNA, DNA, DNA, DNA, DNA) #define RPCC_IMPL \ { \ ! /* FIXME: unimplemented */ \ ! DECLARE_FAULT(md_fault_unimpl); \ } ! DEFINST(RPCC, 0x0c, ! "rpcc (unimpl)", "", NA, NA, DNA, DNA, DNA, DNA, DNA) #define _RS_IMPL \ { \ ! /* FIXME: unimplemented */ \ ! DECLARE_FAULT(md_fault_unimpl); \ } ! DEFINST(_RS, 0x0f, ! "rs (unimpl)", "", NA, NA, DNA, DNA, DNA, DNA, DNA) - /* FIXME: should RC be implemented here? */ CONNECT(JMPJSR) --- 2992,3115 ---- NA, F_TRAP, DNA, DNA, DNA, DNA, DNA) + /* + * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) + */ + + #define EXCB_IMPL \ + { \ + /* FIXME: nada... */ \ + } + DEFINST(EXCB, 0x04, + "excb", "", + NA, F_TRAP, + DNA, DNA, DNA, DNA, DNA) + + #define MB_IMPL \ { \ /* FIXME: not supported... */ \ } ! DEFINST(MB, 0x40, /* -- Changed from 0x04 */ "mb", "", NA, F_TRAP, DNA, DNA, DNA, DNA, DNA) + /* + * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) + */ + + #define WMB_IMPL \ + { \ + /* FIXME: not supported... */ \ + } + DEFINST(WMB, 0x44, + "wmb", "", + NA, F_TRAP, + DNA, DNA, DNA, DNA, DNA) + + + /* -- Changed from unimplemented to unsupported */ #define FETCH_IMPL \ { \ ! /* FIXME: not supported ... */ \ } ! DEFINST(FETCH, 0x80, /* -- Changed from 0x08 */ ! "fetch", "0(b)", NA, NA, DNA, DNA, DNA, DNA, DNA) + /* -- Changed from unimplemented to unsupported */ #define FETCH_M_IMPL \ { \ ! /* FIXME: not supported ... */ \ } ! DEFINST(FETCH_M, 0xa0, /* -- Changed from 0x0a */ ! "fetch_m", "0(b)", NA, NA, DNA, DNA, DNA, DNA, DNA) + /* -- Changed from unimplemented */ #define RPCC_IMPL \ { \ ! /* FIXME: dumb implementation */ \ ! SET_GPR(RA, ULL(0)); \ ! } ! DEFINST(RPCC, 0xc0, /* -- Changed from 0x0c */ ! "rpcc", "a", ! NA, NA, ! DGPR(RA), DNA, DNA, DNA, DNA) ! ! /* ! * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) ! */ ! ! #define _RC_IMPL \ ! { \ ! /* FIXME: not supported */ \ } ! DEFINST(_RC, 0xe0, ! "rc", "a", NA, NA, DNA, DNA, DNA, DNA, DNA) + /* + * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) + */ + + #define ECB_IMPL \ + { \ + /* FIXME: nada... */ \ + } + DEFINST(ECB, 0xe8, + "ecb", "(b)", + NA, NA, + DNA, DNA, DNA, DNA, DNA) + + + /* -- Changed from unimplemented to unsupported */ #define _RS_IMPL \ { \ ! /* FIXME: not supported */ \ } ! DEFINST(_RS, 0xf0, /* -- Changed from 0x0f */ ! "rs", "a", ! NA, NA, ! DNA, DNA, DNA, DNA, DNA) ! ! /* ! * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) ! */ ! ! #define WH64_IMPL \ ! { \ ! /* FIXME: nada... */ \ ! } ! DEFINST(WH64, 0xf8, ! "wh64", "(b)", NA, NA, DNA, DNA, DNA, DNA, DNA) CONNECT(JMPJSR) *************** *** 2857,2866 **** --- 3159,3910 ---- DGPR(RA), DNA, DGPR(RB), DNA, DNA) + /* --Changed from EXTS to FPTI to include more extensions (FIX,CIX,MVI) */ + CONNECT(FPTI) + + /* EV56 BWX extension... */ + DEFLINK(SEXTB_LINK, 0x00, "sextb_link", 12, 1) + + /* EV56 BWX extension... */ + DEFLINK(SEXTW_LINK, 0x01, "sextw_link", 12, 1) + + /* + * -- Added 02/27/99, plakal@cecil, from Alpha Architecture Handbook (Rev.4, EV6) + */ + + /* -- CIX extensions */ + + /* + * -- FIXME: could write a faster version of 1-bit-counting: + * -- i.e., count = 0; while( n ) { n = n & (n-1); count++; } + */ + #define CTPOP_IMPL \ + { \ + int _temp, _i; \ + quad_t _quadhold = GPR(RB); \ + \ + _temp = 0; \ + for( _i = 0; _i <= 63; _i++ ) \ + if( _quadhold & (ULL(1) << _i)) \ + _temp++; \ + \ + SET_GPR(RC, (quad_t)_temp ); \ + } + DEFINST(CTPOP, 0x30, + "ctpop", "b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + + /* -- MVI extensions */ + + #define PERR_IMPL \ + { \ + int _i; \ + quad_t _sum_diffs, _quadhold_a, _quadhold_b; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = GPR(RB); \ + _sum_diffs = 0; \ + \ + for( _i = 0; _i <= 7; _i++ ) \ + { \ + byte_t _bytehold_a, _bytehold_b; \ + \ + _bytehold_a = (_quadhold_a >> (_i*8)) & 0xff; \ + _bytehold_b = (_quadhold_b >> (_i*8)) & 0xff; \ + if( _bytehold_a >= _bytehold_b ) \ + _sum_diffs += (_bytehold_a - _bytehold_b); \ + else \ + _sum_diffs += (_bytehold_b - _bytehold_a); \ + } \ + \ + SET_GPR(RC, _sum_diffs ); \ + } + DEFINST(PERR, 0x31, + "perr", "a,b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA) + + + /* -- CIX extensions */ + + #define CTLZ_IMPL \ + { \ + int _temp, _i; \ + quad_t _quadhold = GPR(RB); \ + \ + _temp = 0; \ + for( _i = 63; _i >= 0; _i-- ) \ + { \ + if( _quadhold & (ULL(1) << _i)) \ + break; \ + \ + _temp++; \ + } \ + \ + SET_GPR(RC, (quad_t)_temp ); \ + } + DEFINST(CTLZ, 0x32, + "ctlz", "b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + #define CTTZ_IMPL \ + { \ + int _temp, _i; \ + quad_t _quadhold = GPR(RB); \ + \ + _temp = 0; \ + for( _i = 0; _i <= 63; _i++ ) \ + { \ + if( _quadhold & (ULL(1) << _i)) \ + break; \ + \ + _temp++; \ + } \ + \ + SET_GPR(RC, (quad_t)_temp ); \ + } + DEFINST(CTTZ, 0x33, + "cttz", "b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + + /* -- MVI extensions */ + + #define UNPKBW_IMPL \ + { \ + quad_t _temp, _quadhold; \ + \ + _temp = 0; \ + _quadhold = GPR(RB); \ + \ + _temp |= (_quadhold & 0xff); \ + _temp |= ( ( (_quadhold >> 8) & 0xff) << 16); \ + _temp |= ( ( (_quadhold >> 16) & 0xff) << 32); \ + _temp |= ( ( (_quadhold >> 24) & 0xff) << 48); \ + \ + SET_GPR(RC, _temp); \ + } + DEFINST(UNPKBW, 0x34, + "unpkbw", "b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + + #define UNPKBL_IMPL \ + { \ + quad_t _temp, _quadhold; \ + \ + _temp = 0; \ + _quadhold = GPR(RB); \ + \ + _temp |= (_quadhold & 0xff); \ + _temp |= ( ( (_quadhold >> 8) & 0xff) << 32); \ + \ + SET_GPR(RC, _temp); \ + } + DEFINST(UNPKBL, 0x35, + "unpkbl", "b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + + #define PKWB_IMPL \ + { \ + quad_t _temp, _quadhold; \ + \ + _temp = 0; \ + _quadhold = GPR(RB); \ + \ + _temp |= (_quadhold & 0xff); \ + _temp |= ( ( (_quadhold >> 16) & 0xff) << 8); \ + _temp |= ( ( (_quadhold >> 32) & 0xff) << 16); \ + _temp |= ( ( (_quadhold >> 48) & 0xff) << 24); \ + \ + SET_GPR(RC, _temp); \ + } + DEFINST(PKWB, 0x36, + "pkwb", "b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + + #define PKLB_IMPL \ + { \ + quad_t _temp, _quadhold; \ + \ + _temp = 0; \ + _quadhold = GPR(RB); \ + \ + _temp |= (_quadhold & 0xff); \ + _temp |= ( ( (_quadhold >> 32) & 0xff) << 8); \ + \ + SET_GPR(RC, _temp); \ + } + DEFINST(PKLB, 0x37, + "pklb", "b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + /* -- Following MVI entries were script-generated :) */ + + DEFLINK(MINSB8_LINK, 0x38, "minsb8_link", 12, 1) + + DEFLINK(MINSW4_LINK, 0x39, "minsw4_link", 12, 1) + + DEFLINK(MINUB8_LINK, 0x3a, "minub8_link", 12, 1) + + DEFLINK(MINUW4_LINK, 0x3b, "minuw4_link", 12, 1) + + DEFLINK(MAXUB8_LINK, 0x3c, "maxub8_link", 12, 1) + + DEFLINK(MAXUW4_LINK, 0x3d, "maxuw4_link", 12, 1) + + DEFLINK(MAXSB8_LINK, 0x3e, "maxsb8_link", 12, 1) + + DEFLINK(MAXSW4_LINK, 0x3f, "maxsw4_link", 12, 1) + + + /* -- FIX extensions */ + + #define FTOIT_IMPL \ + { \ + SET_GPR(RC, FPR_Q(RA)); \ + } + DEFINST(FTOIT, 0x70, + "ftoit", "A,c", + FloatCVT, F_FCOMP, /* -- FIXME: are these flags correct? */ + DGPR(RC), DNA, DFPR(RA), DNA, DNA) + + #define FTOIS_IMPL \ + { \ + squad_t _longhold; \ + sword_t _inthold; \ + \ + _longhold = FPR_Q(RA); \ + _inthold = (((_longhold >> 32) & ULL(0xc0000000)) \ + | ((_longhold >> 29) & ULL(0x3fffffff))); \ + \ + SET_GPR(RC, (SEXT32(_longhold >> 63) << 32) | _inthold ); \ + } + DEFINST(FTOIS, 0x78, + "ftois", "A,c", + FloatCVT, F_FCOMP, /* -- FIXME: are these flags correct? */ + DGPR(RC), DNA, DFPR(RA), DNA, DNA) + + + /* -- MVI extensions (contd) */ + + CONNECT(MINSB8_LINK) + + #define MINSB8_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = GPR(RB); \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 7; _i++ ) \ + { \ + sbyte_t _bytehold_a, _bytehold_b, _bytehold_c; \ + \ + _bytehold_a = (_quadhold_a >> (_i * 8)) & 0xff; \ + _bytehold_b = (_quadhold_b >> (_i * 8)) & 0xff; \ + _bytehold_c = MIN(_bytehold_a, _bytehold_b); \ + \ + _quadhold_c |= (((quad_t)(byte_t)_bytehold_c & 0xff) << (_i*8)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MINSB8, 0x00, + "minsb8", "a,b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA) + + #define MINSB8I_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = IMM ; \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 7; _i++ ) \ + { \ + sbyte_t _bytehold_a, _bytehold_b, _bytehold_c; \ + \ + _bytehold_a = (_quadhold_a >> (_i * 8)) & 0xff; \ + _bytehold_b = (_quadhold_b >> (_i * 8)) & 0xff; \ + _bytehold_c = MIN(_bytehold_a, _bytehold_b); \ + \ + _quadhold_c |= (((quad_t)(byte_t)_bytehold_c & 0xff) << (_i*8)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MINSB8I, 0x01, + "minsb8", "a,i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DGPR(RA), DNA, DNA) + + CONNECT(MINSW4_LINK) + + #define MINSW4_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = GPR(RB); \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 3; _i++ ) \ + { \ + shalf_t _halfhold_a, _halfhold_b, _halfhold_c; \ + \ + _halfhold_a = (_quadhold_a >> (_i * 16)) & 0xffff; \ + _halfhold_b = (_quadhold_b >> (_i * 16)) & 0xffff; \ + _halfhold_c = MIN(_halfhold_a, _halfhold_b); \ + \ + _quadhold_c |= (((quad_t)(half_t)_halfhold_c & 0xffff) << (_i*16)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MINSW4, 0x00, + "minsw4", "a,b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA) + + #define MINSW4I_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = IMM ; \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 3; _i++ ) \ + { \ + shalf_t _halfhold_a, _halfhold_b, _halfhold_c; \ + \ + _halfhold_a = (_quadhold_a >> (_i * 16)) & 0xffff; \ + _halfhold_b = (_quadhold_b >> (_i * 16)) & 0xffff; \ + _halfhold_c = MIN(_halfhold_a, _halfhold_b); \ + \ + _quadhold_c |= (((quad_t)(half_t)_halfhold_c & 0xffff) << (_i*16)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MINSW4I, 0x01, + "minsw4", "a,i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DGPR(RA), DNA, DNA) + + CONNECT(MINUB8_LINK) + + #define MINUB8_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = GPR(RB); \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 7; _i++ ) \ + { \ + byte_t _bytehold_a, _bytehold_b, _bytehold_c; \ + \ + _bytehold_a = (_quadhold_a >> (_i * 8)) & 0xff; \ + _bytehold_b = (_quadhold_b >> (_i * 8)) & 0xff; \ + _bytehold_c = MIN(_bytehold_a, _bytehold_b); \ + \ + _quadhold_c |= (((quad_t)(byte_t)_bytehold_c & 0xff) << (_i*8)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MINUB8, 0x00, + "minub8", "a,b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA) + + #define MINUB8I_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = IMM ; \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 7; _i++ ) \ + { \ + byte_t _bytehold_a, _bytehold_b, _bytehold_c; \ + \ + _bytehold_a = (_quadhold_a >> (_i * 8)) & 0xff; \ + _bytehold_b = (_quadhold_b >> (_i * 8)) & 0xff; \ + _bytehold_c = MIN(_bytehold_a, _bytehold_b); \ + \ + _quadhold_c |= (((quad_t)(byte_t)_bytehold_c & 0xff) << (_i*8)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MINUB8I, 0x01, + "minub8", "a,i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DGPR(RA), DNA, DNA) + + CONNECT(MINUW4_LINK) + + #define MINUW4_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = GPR(RB); \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 3; _i++ ) \ + { \ + half_t _halfhold_a, _halfhold_b, _halfhold_c; \ + \ + _halfhold_a = (_quadhold_a >> (_i * 16)) & 0xffff; \ + _halfhold_b = (_quadhold_b >> (_i * 16)) & 0xffff; \ + _halfhold_c = MIN(_halfhold_a, _halfhold_b); \ + \ + _quadhold_c |= (((quad_t)(half_t)_halfhold_c & 0xffff) << (_i*16)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MINUW4, 0x00, + "minuw4", "a,b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA) + + #define MINUW4I_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = IMM ; \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 3; _i++ ) \ + { \ + half_t _halfhold_a, _halfhold_b, _halfhold_c; \ + \ + _halfhold_a = (_quadhold_a >> (_i * 16)) & 0xffff; \ + _halfhold_b = (_quadhold_b >> (_i * 16)) & 0xffff; \ + _halfhold_c = MIN(_halfhold_a, _halfhold_b); \ + \ + _quadhold_c |= (((quad_t)(half_t)_halfhold_c & 0xffff) << (_i*16)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MINUW4I, 0x01, + "minuw4", "a,i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DGPR(RA), DNA, DNA) + + CONNECT(MAXUB8_LINK) + + #define MAXUB8_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = GPR(RB); \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 7; _i++ ) \ + { \ + byte_t _bytehold_a, _bytehold_b, _bytehold_c; \ + \ + _bytehold_a = (_quadhold_a >> (_i * 8)) & 0xff; \ + _bytehold_b = (_quadhold_b >> (_i * 8)) & 0xff; \ + _bytehold_c = MAX(_bytehold_a, _bytehold_b); \ + \ + _quadhold_c |= (((quad_t)(byte_t)_bytehold_c & 0xff) << (_i*8)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MAXUB8, 0x00, + "maxub8", "a,b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA) + + #define MAXUB8I_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = IMM ; \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 7; _i++ ) \ + { \ + byte_t _bytehold_a, _bytehold_b, _bytehold_c; \ + \ + _bytehold_a = (_quadhold_a >> (_i * 8)) & 0xff; \ + _bytehold_b = (_quadhold_b >> (_i * 8)) & 0xff; \ + _bytehold_c = MAX(_bytehold_a, _bytehold_b); \ + \ + _quadhold_c |= (((quad_t)(byte_t)_bytehold_c & 0xff) << (_i*8)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MAXUB8I, 0x01, + "maxub8", "a,i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DGPR(RA), DNA, DNA) + + CONNECT(MAXUW4_LINK) + + #define MAXUW4_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = GPR(RB); \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 3; _i++ ) \ + { \ + half_t _halfhold_a, _halfhold_b, _halfhold_c; \ + \ + _halfhold_a = (_quadhold_a >> (_i * 16)) & 0xffff; \ + _halfhold_b = (_quadhold_b >> (_i * 16)) & 0xffff; \ + _halfhold_c = MAX(_halfhold_a, _halfhold_b); \ + \ + _quadhold_c |= (((quad_t)(half_t)_halfhold_c & 0xffff) << (_i*16)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MAXUW4, 0x00, + "maxuw4", "a,b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA) + + #define MAXUW4I_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = IMM ; \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 3; _i++ ) \ + { \ + half_t _halfhold_a, _halfhold_b, _halfhold_c; \ + \ + _halfhold_a = (_quadhold_a >> (_i * 16)) & 0xffff; \ + _halfhold_b = (_quadhold_b >> (_i * 16)) & 0xffff; \ + _halfhold_c = MAX(_halfhold_a, _halfhold_b); \ + \ + _quadhold_c |= (((quad_t)(half_t)_halfhold_c & 0xffff) << (_i*16)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MAXUW4I, 0x01, + "maxuw4", "a,i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DGPR(RA), DNA, DNA) + + CONNECT(MAXSB8_LINK) + + #define MAXSB8_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = GPR(RB); \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 7; _i++ ) \ + { \ + sbyte_t _bytehold_a, _bytehold_b, _bytehold_c; \ + \ + _bytehold_a = (_quadhold_a >> (_i * 8)) & 0xff; \ + _bytehold_b = (_quadhold_b >> (_i * 8)) & 0xff; \ + _bytehold_c = MAX(_bytehold_a, _bytehold_b); \ + \ + _quadhold_c |= (((quad_t)(byte_t)_bytehold_c & 0xff) << (_i*8)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MAXSB8, 0x00, + "maxsb8", "a,b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA) + + #define MAXSB8I_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = IMM ; \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 7; _i++ ) \ + { \ + sbyte_t _bytehold_a, _bytehold_b, _bytehold_c; \ + \ + _bytehold_a = (_quadhold_a >> (_i * 8)) & 0xff; \ + _bytehold_b = (_quadhold_b >> (_i * 8)) & 0xff; \ + _bytehold_c = MAX(_bytehold_a, _bytehold_b); \ + \ + _quadhold_c |= (((quad_t)(byte_t)_bytehold_c & 0xff) << (_i*8)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MAXSB8I, 0x01, + "maxsb8", "a,i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DGPR(RA), DNA, DNA) + + CONNECT(MAXSW4_LINK) + + #define MAXSW4_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = GPR(RB); \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 3; _i++ ) \ + { \ + shalf_t _halfhold_a, _halfhold_b, _halfhold_c; \ + \ + _halfhold_a = (_quadhold_a >> (_i * 16)) & 0xffff; \ + _halfhold_b = (_quadhold_b >> (_i * 16)) & 0xffff; \ + _halfhold_c = MAX(_halfhold_a, _halfhold_b); \ + \ + _quadhold_c |= (((quad_t)(half_t)_halfhold_c & 0xffff) << (_i*16)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MAXSW4, 0x00, + "maxsw4", "a,b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RA), DGPR(RB), DNA) + + #define MAXSW4I_IMPL \ + { \ + int _i; \ + quad_t _quadhold_a, _quadhold_b, _quadhold_c; \ + \ + _quadhold_a = GPR(RA); \ + _quadhold_b = IMM ; \ + _quadhold_c = 0; \ + \ + for( _i = 0; _i <= 3; _i++ ) \ + { \ + shalf_t _halfhold_a, _halfhold_b, _halfhold_c; \ + \ + _halfhold_a = (_quadhold_a >> (_i * 16)) & 0xffff; \ + _halfhold_b = (_quadhold_b >> (_i * 16)) & 0xffff; \ + _halfhold_c = MAX(_halfhold_a, _halfhold_b); \ + \ + _quadhold_c |= (((quad_t)(half_t)_halfhold_c & 0xffff) << (_i*16)); \ + } \ + \ + SET_GPR(RC, _quadhold_c ); \ + } + DEFINST(MAXSW4I, 0x01, + "maxsw4", "a,i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DGPR(RA), DNA, DNA) + + + + /* EV56 BWX extension... */ + CONNECT(SEXTB_LINK) + + /* EV56 BWX extension... */ + #define SEXTB_IMPL \ + { \ + SET_GPR(RC, (quad_t)(squad_t)(sbyte_t)(GPR(RB) & 0xff)); \ + } + DEFINST(SEXTB, 0x00, + "sextb", "b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + /* EV56 BWX extension... */ + #define SEXTBI_IMPL \ + { \ + SET_GPR(RC, (quad_t)(squad_t)(sbyte_t)(IMM & 0xff)); \ + } + DEFINST(SEXTBI, 0x01, + "sextb", "i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DNA, DNA, DNA) + + + /* EV56 BWX extension... */ + CONNECT(SEXTW_LINK) + + /* EV56 BWX extension... */ + #define SEXTW_IMPL \ + { \ + SET_GPR(RC, (quad_t)(squad_t)(shalf_t)(GPR(RB) & 0xffff)); \ + } + DEFINST(SEXTW, 0x00, + "sextw", "b,c", + IntALU, F_ICOMP, + DGPR(RC), DNA, DGPR(RB), DNA, DNA) + + /* EV56 BWX extension... */ + #define SEXTWI_IMPL \ + { \ + SET_GPR(RC, (quad_t)(squad_t)(shalf_t)(IMM & 0xffff)); \ + } + DEFINST(SEXTWI, 0x01, + "sextw", "i,c", + IntALU, F_ICOMP|F_IMM, + DGPR(RC), DNA, DNA, DNA, DNA) + + + /* clean up all definitions... */ #undef LDA_IMPL #undef LDAH_IMPL + #undef LDBU_IMPL #undef LDQ_U_IMPL + #undef LDWU_IMPL + #undef STW_IMPL + #undef STB_IMPL #undef STQ_U_IMPL #undef FLTV_IMPL #undef LDF_IMPL *************** *** 2966,2975 **** --- 4010,4022 ---- #undef CMOVGEI_IMPL #undef EQV_IMPL #undef EQVI_IMPL + #undef AMASK_IMPL + #undef AMASKI_IMPL #undef CMOVLE_IMPL #undef CMOVLEI_IMPL #undef CMOVGT_IMPL #undef CMOVGTI_IMPL + #undef IMPLVER_IMPL #undef MSKBL_IMPL #undef MSKBLI_IMPL #undef EXTBL_IMPL *************** *** 3030,3035 **** --- 4077,4089 ---- #undef MULQI_IMPL #undef UMULH_IMPL #undef UMULHI_IMPL + #undef ITOFS_IMPL + #undef SQRTF_IMPL + #undef SQRTS_IMPL + #undef ITOFF_IMPL + #undef ITOFT_IMPL + #undef SQRTG_IMPL + #undef SQRTT_IMPL #undef ADDS_IMPL #undef SUBS_IMPL #undef MULS_IMPL *************** *** 3060,3074 **** --- 4114,4155 ---- #undef FCMOVGT_IMPL #undef CVTQL_IMPL #undef TRAPB_IMPL + #undef EXCB_IMPL #undef MB_IMPL + #undef WMB_IMPL #undef FETCH_IMPL #undef FETCH_M_IMPL #undef RPCC_IMPL + #undef _RC_IMPL + #undef ECB_IMPL #undef _RS_IMPL + #undef WH64_IMPL #undef JMP_IMPL #undef JSR_IMPL #undef RETN_IMPL #undef JSR_COROUTINE_IMPL + #undef SEXTB_IMPL + #undef SEXTBI_IMPL + #undef SEXTW_IMPL + #undef SEXTWI_IMPL + #undef CTPOP_IMPL + #undef PERR_IMPL + #undef CTLZ_IMPL + #undef CTTZ_IMPL + #undef UNPKBW_IMPL + #undef UNPKBL_IMPL + #undef PKWB_IMPL + #undef PKLB_IMPL + #undef MINSB8_IMPL + #undef MINSW4_IMPL + #undef MINUB8_IMPL + #undef MINUW4_IMPL + #undef MAXUB8_IMPL + #undef MAXUW4_IMPL + #undef MAXSB8_IMPL + #undef MAXSW4_IMPL + #undef FTOIT_IMPL + #undef FTOIS_IMPL #undef DEFINST #undef DEFLINK