Jason Lowe-Power

Ph.D. Candidate
Computer Sciences Department
University of Wisconsin-Madison

Research interests

As a computer architect, I broadly want to enable the continuing exponential growth in computing capability despite the slowing of Moore’s Law. My research interests are heterogeneous systems, memory systems, and hardware-software interaction.

Graduate work

I am currently on the academic job market! You can find some of my materials here: Curriculum Vitae, Research Statement, and Teaching Statement.

I am part of the multifacet group which has historically focused on multicore memory systems. I am advised by Mark Hill and David Wood.

I am one of the main developers of gem5-gpu, a heterogeneous system simulator, and I am a leader in the gem5 ("A modular platform for computer system architecture research") community.

Publications

bullet point When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big-Data Workloads
Jason Lowe-Power, Mark D. Hill, David A. Wood The Seventh Workshop on Big Data Benchmarks, Performance Optimization, and Emerging Hardware (BPOE 7) at ASPLOS April 2016
bullet point Border Control: Sandboxing Accelerators
Lena E. Olson, Jason Power, Mark D. Hill, David A. Wood The 48th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 48 Dec 2015
bullet point Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries
Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, David A. Wood Proceedings of the Eleventh International Workshop on Data Management on New Hardware, DaMoN '15 June 2015
bullet point Implications of Emerging 3D GPU Architecture on the Scan Primitive
Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, David A. Wood SIGMOD Record. Volume 44, Issue 1 March 2015
bullet point Supporting x86-64 Address Translation for 100s of GPU Lanes
Jason Power, Mark D. Hill, David A. Wood The 20th IEEE International Symposium On High Performance Computer Architecture, HPCA 20 Feb 2014
bullet point gem5-gpu: A Heterogeneous CPU-GPU Simulator
Jason Power, Joel Hestness, Marc S. Orr, Mark D. Hill, David A. Wood Computer Architecture Letters vol. 14, no. 1, pp. Jan-June 2015
bullet point Heterogeneous System Coherence for Integrated CPU-GPU Systems
Jason Power, Arkaprava Basu, Junli Gu, Sooraj Puthoor, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, David A. Wood The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 46 Dec 2013
bullet point Learning gem5 (work in progress)
Jason Power

Online book aimed to familiarize new users with the gem5 architectural simulator. This is a current work-in-progress, so check back often for updates.

Presentations

bullet point Tutorial organizer Learning gem5 at HPCA 2017
bullet point Little Shop of gem5 Horrors
Jason Power Second gem5 Users Workshop with ISCA 42 Jun 2015
bullet point Invited talk The Benefits of GPUs for Analytic Processing—Today and Tomorrow
Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, David A. Wood Google Madison June 2015
bullet point BitWarp: Energy Efficient Analytic Data Processing on Next Generation General Purpose GPUs
Jason Power, Mark D. Hill, Yinan Li, Jignesh M. Patel, David A. Wood UW Computer Architecture Affiliates Meeting Oct 2014
bullet point Invited talk Supporting x86-64 Address Translation for 100s of GPU Lanes
Jason Power, Mark D. Hill, David A. Wood AMD Research Feb 2014
bullet point MMUs for GPGPUs: Supporting x86-64 Address Translation for 100s of GPU Lanes
Jason Power, Mark D. Hill, David A. Wood UW Computer Architecture Affiliates Meeting Oct 2013
bullet point Leveraging Future Technology for Energy Efficient Databases (Poster)
Jason Power, Yinan Li, Mark D. Hill, Jignesh Patel, David A. Wood UW Computer Architecture Affiliates Meeting Oct 2013
bullet point gem5-gpu: A Simulator for Heterogeneous Processors
Jason Power, Marc S. Orr, Joel Hestness, Mark D. Hill, David A. Wood First Annual gem5 User Workshop with MICRO 45 Dec 2012
bullet point G3 (gem5+GPGPU-Sim): A Simulator for Heterogeneous Processors (Poster)
Jason Power, Marc S. Orr, David A. Wood UW Computer Architecture Affiliates Meeting Oct 2011

Awards

bullet point

Cisco Systems Distinguished Graduate Fellowship

2014–2015 & 2015–2016
bullet point

Summer Research Assistant Award

Summer 2011

Proposal title: Exploring Cache Coherence on GPGPUs

Teaching

Lecturer: CS 354 (Machine Organization and Programming)

Fall 2015

Lectured to class of 141 three times weekly. Prepared teaching material, tests, and assignments. Course website

Guest Lectures: CS 752 (Advanced Computer Architecture I) DRAM, Memory Systems, and Virtualization

Spring 2015

Presented a class on main memory including a discussion of DRAM architecture and memory system policies.

Presented a class on virtual memory including a discussion of paging, translation, TLBs, and virtual memory system performance.

Presented a class on virtual machine support including a discussion of nested paging and current research proposals for reducing virtual memory overheads.

Guest Lectures: CS 757 (Advanced Computer Architecture II) GPU Architectures and Memory Systems

Spring 2014

Presented a class on GPU architecture including data parallelism, GPU execution models, GPU programming models, and modern GPU architecture.

Presented a class on GPU memory systems including a discussion of modern memory system design and recent research proposals including QuickRelease, Heterogeneous Race Free memory model, Heterogeneous System Coherence, and Supporting Address Translation for 1000's of GPU Lanes.

Math Teaching Assistant in Georgia Tech Math Department

Fall 2007

Taught Honors Calculus I to class of 32 twice weekly and assisted students one-on-one.

Work Experience

Intern at Advanced Micro Devices (AMD) Research

Spring 2012

Explored new cache coherence architectures to support future heterogeneous CPU-GPU processors. The publication Heterogeneous System Coherence for Integrated CPU-GPU Systems (HSC) is a result of this work.

Applied for patent "Serving memory requests in cache coherent heterogeneous systems" that describes an optmization to HSC for producer-consumer sharing on heterogeneous systems.

Co-op at Georgia Tech Research Institute (GTRI)

2008–2009

Built large Windows software application as part of a team to monitor subsystems in modern fighter jets and developed software for embedded machines running VxWorks which controlled electronic warfare systems.

Acquired Secret Security Clearance

Volunteer and Outreach

Scratch Club for 5th Graders

Fall 2014

Taught an after school class of 16 5th graders the basics of computer science as part of a team. Helped develop lesson plans and taught the whole class and students one-on-one.

40 Years of Computer Architecture

Fall 2014

Created a poster which details professors, graduates, and their awards throughout the history of the computer architecture program at UW-Madison.

Education

Master of Science in Computer Science

University of Wisconsin-Madison Summer 2013

Bachelor of Science in Computer Science

Georgia Institute of Technology Summa cum laude Spring 2010

Contact

Email:

powerjg@cs.wisc.edu

Office:

Office 6366
Computer Sciences Building
1210 W Dayton St.
Madison, WI 53706