Gurindar S. Sohi

Professor of Computer Sciences and Electrical and Computer Engineering and Vilas Associate

Computer Sciences Department
University of Wisconsin
1210 W. Dayton St.
Madison, WI 53706-1685

telephone: (608) 262-1204
fax: (608) 262-9777
email: sohi@cs.wisc.edu
http://www.cs.wisc.edu/~sohi/

Research Summary

My research focuses on the design of the highest performance uniprocessors of a current generation, along with their supporting memory systems. Most of my research efforts of the past 5 years involved the development of a new paradigm for circa 2000 and beyond processors. These efforts led to the development of the multiscalar paradigm -- a paradigm that has served as the the starting point for over half a dozen major research projects worldwide. My current research efforts are along three broad themes: (i) continuing to develop the multiscalar paradigm, (ii) investigating "beyond multiscalar" issues, i.e., processing issues in the 2005-2010 era, and (iii) understanding program behavior and developing generic mechanisms to exploit it.

In the multiscalar arena, we continue to study memory systems to support multiscalar processing, support to allow the microarchitecture to span the multiscalar-multiprocessor spectrum, software optimizations and support for multiscalar processors, and ways of extracting multiscalar-specific information in a binary compatible manner. In the "beyond multiscalar" arena, we are starting to take a fresh look at memory hierarchies. Whereas the instruction processing model has changed dramatically in the past decade, memory hierarchies have stayed pretty much the same for 2 decades. We are investigating alternate memory hierarchy organizations for the billion-transistor era. We are also beginning to take a look at how other aspects of the computing program, e.g., algorithms and compiling might be different in this era. In the understanding program behavior arena, my research group is looking at the (dynamic) reusability of computation -- why it occurs, and how to exploit it.

Sample Recent Publications

An empirical analysis of instruction repetition (with A. Sodani), Proceedings of the ASPLOS-VIII, San Jose, California, October 1998.

Task partitioning for the multiscalar architecture (with T. Vijaykumar), Proceedings of the 31st International Symposium on Microarchitecture (MICRO-31), Dallas, Texas, December 1998.