David A. Wood

Associate Professor of Computer Sciences and Electrical and Computer Engineering

Computer Sciences Department
University of Wisconsin
1210 W. Dayton St.
Madison, WI 53706-1685

telephone: (608) 262-1204
fax: (608) 262-9777
email: david@cs.wisc.edu
http://www.cs.wisc.edu/~david/
Ph.D., University of California, Berkeley, 1990
Interests: Computer architecture, performance evaluation, parallel processing, VLSI Design

Research Summary

My main research goals lie in developing cost-effective computer architectures that exploit the recent, rapid changes in technology. My research emphasizes performance evaluation and experimental validation to demonstrate an architecture's performance, feasibility, and correctness. A major component of my research program is the Wisconsin Wind Tunnel project (in conjunction with Profs. Hill and Larus), in which we use a parallel simulation system to investigate cost-effective, scalable, parallel computers.

The major thrust of this research has been a new interface - called Tempest - between user-level protocol handlers and system-supplied mechanisms. Tempest provides the mechanisms that allow programmers, compilers, and program libraries to implement and use message passing, transparent shared memory, and hybrid combinations of the two. Tempest mechanisms are low-overhead messages, bulk data transfer, virtual memory management, and fine-grain access control. The most novel mechanism - fine-grain access control - allows user software to tag blocks (e.g., 32 bytes) as read-write, read-only, or invalid, so the local memory can be used to transparently cache remote data.

We have been exploring alternative ways to support this interface. The first - called Typhoon - is a proposed hardware platform that implements the Tempest mechanisms with a fully-programmable, user-level processor in the network interface. The second - called Blizzard - uses a combination of hardware and software to support this interface on the department's Thinking Machines CM-5 and Cluster Of Workstations (COW). We have begun porting Blizzard to the IBM SP-2. We have also developed a third implementation - called Typhoon-0 - that extends the COW nodes with a special hardware module.

Sample Recent Publications

Reactive NUMA: A design for unifying S-COMA and CC-NUMA (with B. Falsafi), Proceedings of the 24th International Symposium on Computer Architecture, 1997.

Scheduling communication on an SMP node parallel machine (with B. Falsafi), Proceedings of the International Symposium on High Performance Computer Architecture, 1997.

Active memory: A new abstraction for memory system simulation (with A. Lebeck), ACM Transactions on Modeling and Computer Simulation, vol. 7, no. 1, pp. 42-77, 1997.

This page was automatically created December 30, 1998.
Email pubs@cs.wisc.edu to report errors.