Participant Bios

Bradley Kuszmaul

Bradley C. Kuszmaul received a Ph.D. from MIT in 1993. He took two years off from graduate school to act as one of the principal architects of the Connection Machine CM-5 supercomputer at Thinking Machines Corporation. He was an Assistant Professor in the Department of Computer Science at Yale University from 1995 through 2001, where he investigated on asymptotically optimal circuits for out-of-order superscalar processors. In 2000, he joined Akamai Technologies, Inc., as a Senior Research Scientist, where he lead the development of the network usage billing system. In 2002, he returned to MIT as a research scientist in the Supercomputing Technologies research group of the Computer Science and Artificial Intelligence Laboratory (CSAIL). He is investigating transactional memory and the problem of laying out huge databases on disk to achieve good performance.

Brian Bershad

Brian Bershad , Associate Professor, has been at the University of Washington since 1986. After receiving his PhD from the University of Washington in 1990, he took a brief respite from Seattle between 1990 and 1993 to experiment with post-industrial culture in the Northeast. In 1993, he returned to the Northwest for the coffee.   

Bershad does research in operating systems, distributed systems, networking, parallel systems, and architecture. A lot of his work has appeared in TOCS, SOSP, ASPLOS and ISCA, although he can't seem to get a SIGMETRICS paper published to save his life.

Charles Leiserson

Charles E. Leiserson received the B.S. degree in computer science and mathematics from Yale University, New Haven, Connecticut, in 1975 and the Ph.D. degree in computer science from Carnegie Mellon University, Pittsburgh, Pennsylvania, in 1981. In 1981, he joined the faculty of the Massachusetts Institute of Technology, Cambridge, Massachusetts. He is now Professor of Computer Science and Engineering in the MIT Department of Electrical Engineering and Computer Science and member of the Theory of Computation research group in the MIT Laboratory for Computer Science. He holds an Adjunct Professorship at the National University of Singapore and the positions of Director of System Architecture, Director of Research, and Network Architect at Akamai Technologies, Inc. of Cambridge, Massachusetts. He is the Director of the Computer Science Program of the Singapore-MIT Alliance, a distance-education initiative in which students in Singapore take MIT classes.

Prof. Leiserson's research centers on developing theoretical principles of parallel and distributed computing, especially as they relate to engineering reality. Prof. Leiserson pioneered the development of VLSI theory and has written many papers on VLSI algorithms, graph layout, and computer-aided design. His contributions include the divide-and-conquer method of graph layout and the retiming method for optimizing digital circuitry. Prof. Leiserson has been a leader in the development of parallel computing. As a graduate student at Carnegie Mellon, he wrote the first paper on systolic architectures with his advisor H.T. Kung. While Corporate Fellow of Thinking Machines Corporation, he designed and led the implementation of the network architecture for the Connection Machine Model CM-5 Supercomputer, which incorporates the fat-tree interconnection network he developed at MIT. He has designed and engineered many parallel algorithms, including ones for matrix linear algebra, graph algorithms, optimization, and sorting.

Prof. Leiserson's recent research has focused on dynamic, asynchronous parallel computing. His Cilk multithreaded language features a provably good work-stealing scheduler that guarantees the efficient execution of user programs. He and his research group designed and implemented the StarTech, *Socrates, and Cilkchess parallel chess-playing programs, which have won numerous prizes in international competition. A team of Cilk programmers led by Prof. Leiserson won First Prize in the 1998 ICFP Programming Contest sponsored by the International Conference on Functional Programming, in which Cilk was declared to be ``the programming language of choice for discriminating hackers.'' His Cilk work also inspired the creation of efficiently implementable distributed-memory consistency models, as well as ``cache-oblivious'' algorithms which exploit available processor caches efficiently without any tuning of cache-dependent parameters.

Prof. Leiserson's academic work has won many awards. His Ph.D. dissertation, Area-Efficient VLSI Computation, which deals with the design of systolic systems and with the problem of determining the VLSI area of a graph, won the first ACM Doctoral Dissertation Award in 1981, as well as the Fannie and John Hertz Foundation Doctoral Thesis Award. In 1985 he received a Presidential Young Investigator Award from the National Science Foundation. Three of his papers have received awards from the IEEE International Conference on Parallel Processing. His textbook, Introduction to Algorithms, coauthored with Ronald L. Rivest and Thomas H. Cormen, was named Best 1990 Professional and Scholarly Book in Computer Science and Data Processing by the Association of American Publishers. The textbook, now in its second edition with an additional coauthor, Clifford Stein, is currently the leading textbook on computer algorithms.

Prof. Leiserson is a member of the ACM, IEEE, and SIAM. In 1995-6, he was Shaw Visiting Professor in the Department of Information Systems and Computer Science at the National University of Singapore. A dedicated teacher, Prof. Leiserson has directly supervised 20 Ph.D. students and over 50 master's and bachelor's students.

Christos Kozyrakis

Christos Kozyrakis is an assistant professor of Electrical Engineering  and Computer Science at Stanford University. He received a Ph.D. in  Computer Science from U.C. Berkeley where he architected the Vector IRAM  media processor. Christos’ research focuses on architectures, compilers,  and programming models for parallel computer systems. He is currently  the co-leader of the Stanford Transactional Coherence and Consistency (TCC) project, which investigates parallel programming and execution  based exclusively on hardware supported transactions. 

Cormac Flanagan

Cormac Flanagan is an Assistant Professor at the University of California at Santa Cruz and an Alfred P. Sloan Research Fellow. He was previously a research scientist for Digital, Compaq, and HP. His research focuses on static and dynamic checking tools that improve program reliability and reduce development cost, with a particular focus on concurrent software systems. He received his Ph.D. from Rice University in 1997. For more information, see http://www.soe.ucsc.edu/~cormac/.

Dan Grossman

Dan Grossman is an Assistant Professor at the University of Washington. He received his Ph.D. from Cornell University in 2003. His research is in the areas of programming language design and implementation. He is best known for Cyclone, a type-safe language that is very much like C. More recently he has been investigating software-based implementations for atomicity in high-level programming languages.

Homepage: http://www.cs.washington.edu/homes/djg

David Gay

David Gay obtained his PhD from the University of California at Berkeley in 2001, where he worked on parallel languages for scientific computing and region-based memory management. Since then, he has been working at Intel Research Berkeley on programming languages (nesC) and operating systems (TinyOS) for sensor networks.

David Wood

Prof. David A. Wood is a Professor and Romnes Fellow in the Computer Sciences Department at the University of Wisconsin, Madison. Dr. Wood also holds a courtesy appointment in the Department of Electrical and Computer Engineering. Dr. Wood received a B.S. in Electrical Engineering and Computer Science (1981) and a Ph.D. in Computer Science (1990), both at the University of California, Berkeley. He joined the faculty at the University of Wisconsin in 1990.

Dr. Wood was named a Fellow of the IEEE (2004), received the University of Wisconsin's H.I. Romnes Faculty Fellowship (1999), and received the National Science Foundation's Presidential Young Investigator award (1991). Dr. Wood is Area Editor (Computer Systems) of ACM Transactions on Modeling and Computer Simulation, is Associate Editor of ACM Transactions on Architecture and Compiler Optimization, served as Program Committee Chairman of ASPLOS-X (2002), and has served on numerous program committees. Dr. Wood is a member of ACM, an IEEE Fellow, and member of the IEEE Computer Society. Dr. Wood has published over 70 technical papers and is an inventor on seven U.S. and International patents.

Dr. Wood co-leads the Wisconsin Multifacet project with Prof. Mark Hill (URL http://www.cs.wisc.edu/multifacet) which is exploring techniques for improving the availability, designability, programmability, and performance of commercial multiprocessor and chip multiprocessor servers.

Eliot Moss

Eliot Moss received his undergraduate and graduate degrees from the Massachusetts Institute of Technology, culminating in a Ph.D. in computer science in 1981, on the subject of nested transactions. He served in the U.S. Army until 1985 when he joined the faculty of the Department of Computer Science, University of Massachusetts at Amherst, where he now holds the rank of Associate Professor. He co-directs the Architecture and Language Implementation Laboratory, which is concerned with the implementation and performance of modern languages (such as Java) on modern
hardware platforms. 

Related to his PhD work on nested transactions, with Maurice Herlihy he devised Transactional Memory, presented at the International Symposium on Computer Architecture in 1993 and patented in 1995. Related work includes papers on lock-free garbage collection and, more recently, the Sapphire concurrent garbage collector. In transaction models, Dr. Moss has contributed not only to the "closed" nesting model, but also to the proper semantics of the open nesting model, also called multi-level transactions.

Geoff Lowney

Geoffrey Lowney is an Intel Fellow, Enterprise Platforms Group and Director of Compiler and Architecture Advanced Development. He is responsible for using advanced compiler technology to improve the performance of future Intel® Itanium® processor family products.

Lowney joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel.

Prior to joining Intel, he was a Compaq Fellow and Director of Compiler and Architecture Development for the Alpha Microprocessor Group. His responsibilities included developing compiler technology and tuning compilers for Alpha systems, providing architectural direction to the microprocessor design teams and designing Alpha architecture extensions.

Before joining Digital Equipment Corporation in 1991, Lowney was a Consulting Engineer at Hewlett-Packard from 1990 to 1991. From 1984 to 1990, he was Director of Compiler Development at Multiflow Computer.

Lowney received his doctorate and master's degrees in computer science and his bachelor's degree in mathematics from Yale University in 1983, 1978 and 1975, respectively. He holds six patents with an additional six patent disclosures filed.

Guri Sohi

Guri Sohi received a Ph.D in Electrical and Computer Engineering from the University of Illinois, and has been a faculty member at the University of Wisconsin-Madison since 1985. He is currently the Chair of the Computer Sciences department. 

Sohi's research has been in the design of high-performance computer systems. He has co-authored several papers and patents that have influenced both researchers and commercial microprocessors. Topics that he has investigated in the past or continues to investigate include include dynamically-scheduled instruction-level parallel processors, out-of-order execution with precise exceptions, non-blocking caches, decentralized microarchitectures, speculative multithreading, computation reuse, memory dependence speculation and prediction, value degree of use prediction. 

Sohi has interacted heavily with industry. Over the years he has discussed his research with architects and given talks in design groups at most of the leading microprocessor manufacturers in industry, including Cray Research, Digital Equipment, HaL, Hewlett-Packard, IBM, Intel, MIPS, Motorola, Silicon Graphics, and Sun Microsystems. 

Sohi has graduated 13 Ph.D students, many of whom currently hold academic positions at leading research universities (Illinois, Maryland, Michigan, Pennsylvania, Purdue, and Toronto). They include six winners of NSF NYI/CAREER awards and a winner of a Sloan Research Fellowship. He received the 1999 ACM SIGARCH Maurice Wilkes award "for seminal contributions in the areas of high issue rate processors and instruction level parallelism". At the University of Wisconsin he was selected as a Vilas Associate in 1997 and won the WARF Kellett Mid-Career Faculty Researcher award in 2000.

Jesse Fang

Jesse is director and chief scientist of Programming System Lab (PSL) in Intel Microprocessor Technology Labs (MTL). PSL has about 40 researchers. The primary goals of PSL are (1) to explore programming system technologies to drive/enable uArchitecture research and microprocessor design within Intel, and (2) to develop leading-position optimizations on Intel current processor and then to transfer the technologies to Intel Software Division, Independent Software Vendors (ISVs) and open source community. Jesse set up the research direction, recruited senior researchers, and grew up PSL since he joined Intel in 1995. A number of significant research results have been developed from his lab such as Intel Managed Runtime on IA-32/IPF/XScale, Open IPF Research Compiler, Managed Runtime Enabling uArch features, Binary Translation for low-power IA and Speculative Multithreading technologies. He built compiler/runtime team at Intel China Research Center in Beijing as well. PSL has over 80 publications in the top-level computer conference like ISCA, PLDI, Micro, PACT and HPCA. PSL has more that 200 patent disclosures.

Before Intel, Jesse was working on Hewlett-Packet Research Labs (HP Labs) since 1990. He was one of architects in design of Intel/HP joint Itanium architecture, and led compiler/system software team at HP Labs. Between Intel and HP, Jesse was co-funder and CTO for a start-up. Before HP Labs, Jesse worked on vector compiler on supercomputer at Convex Computer Corp. since 1988 and real-time OS at Concurrent Computer Corp. since 1986 respectively. Before industry, Jesse was associate professor at Kansas State University after he did post-doctor at Center of Supercomputing Research and Development (CSRD) at Univ. of Illinois. Jesse got his Ph.D. in Computer Science at Univ. of Nebraska Lincoln.

Jim Goodman

James R. Goodman received the Ph.D. from the University of California at Berkeley in 1980. From 1974-80 he worked for Intel Corporation, designing add-on memory systems for main frames and developing specifications for processor and memory components. From 1980-2004 he was a member of the faculty at the University of Wisconsin-Madison, where he is now an emeritus professor. He is currently a professor of Computer Science at the University of Auckland, New Zealand.

Goodman was an early contributor to the multiprocessor snooping cache literature, and published the first paper to describe a snooping algorithm. He and others proposed the first queue-based locking protocol (QOLB). He has published papers in the area of cache coherence algorithms and shared memory multiprocessor architectures, database systems, interconnection networks, virtual memory, memory-register organization, memory systems design, and novel multiprocessor architectures. His current research is focused on multiprocessor memory hierarchies and synchronization.

He is the co-author of an undergraduate textbook, entitled, "A Programmer's View of Computer Architecture."

Jim Larus

I am currently a Senior Researcher in Microsoft Research, managing the Software Improvement Group (SWIG), which consists of the SPT, TVM, and HIP research groups, and running the Singularity research project. At Microsoft Research, I started and, for five years, led the Software Productivity Tools (SPT) group, which is one of the most innovative and productive groups currently working in the area of program analysis and programming tools. Before joining Microsoft, I was an Associate Professor at the University of Wisconsin-Madison, where I co-led the Wisconsin Wind Tunnel research project with Professors Mark Hill and David Wood. This DARPA and NSF-funded project investigated new approaches to building and programming parallel shared-memory computers. While at Wisconsin, I received an NSF Young Investigator award in 1993. I received my PhD from the University of California, Berkeley in 1989.

Jim Johnson

Jim Johnson is the architect for transaction services in the Indigo group. As such, Jim is responsible for both the traditional Windows transaction manager (MSDTC), and the more recent .Net 2.0 feature, System.Transactions. Prior to joining Microsoft, Jim spent most of the previous 20 years in various base systems software groups. During that time, Jim led the implementation on the transaction management services in the OpenVMS operating system kernel, as well as a variety of other areas.

John Crawford

John H. Crawford is an Intel Fellow at the Intel Corporation, Santa Clara, California, where he investigates emerging technology directions and issues for future Itanium® Processor Family products. Mr. Crawford was the Chief Architect of both the Intel386™ and Intel486™ microprocessors, and co-project manager of the Pentium® microprocessor. He managed the joint Intel/HP team that defined the Itanium Processor Family instruction set architecture, and directed aspects of Itanium processor product development.

 Mr. Crawford was awarded the ACM/IEEE Eckert-Mauchly Award, and the IEEE Ernst Weber Engineering Leadership Recognition. He was elected to the National Academy of Engineering in 2002.

Konrad Lai

Konrad Lai received the BSE from Princeton University and MSCE from Carnegie Mellon University. He is currently a Senior Principal Research Scientist in the Microprocessor Technology Laboratories, Intel Corporation. He has been with Intel for over 25 years, working on object oriented architecture, microprocessor, multiprocessor system, memory technology, and system architecture.

His current research interests include advanced microarchitecture, FPGA prototype, and hardware/software support for multi/many-core architecture.

Krste Asanovic

Krste Asanovic is an Associate Professor in the MIT Department of Electrical Engineering and Computer Science, and a member of the MIT Computer Science and Artificial Intelligence Laboratory. He received a B.A. in Electrical and Information Sciences from Cambridge University in 1987 and a Ph.D. in Computer Science from UC Berkeley in 1998. His primary research interests are computer architecture and VLSI design. His current projects include the SCALE vector-thread architecture for energy-efficient high-performance embedded computing, Mondriaan Memory Protection to enforce word-granularity software module boundaries, and the InfiniT architecture for highly threaded and transactional parallel computing.

Kunle Olukotun

Kunle Olukotun is an Associate Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun received his Ph.D. in from The University of Michigan. Olukotun led the Stanford Hydra single-chip multiprocessor research project which developed a novel architecture for combining multiple processors on a single chip which included support for thread-level speculation. Olukotun founded Afara Websystems to develop commercial server systems with chip multiprocessor technology. Afara was acquired by Sun Microsystems; the Afara processor technology, called Niagara, will appear in future Sun products. Olukotun currently leads projects in computer architecture, parallel programming environments and formal hardware verification.

Mark Hill

Mark D. Hill (http://www.cs.wisc.edu/~markhill) is Professor in both the Computer Sciences Department and the Electrical and Computer Engineering Department at the University of Wisconsin - Madison. Dr. Hill's research targets the memory systems of shared-memory multiprocessors and high-performance uniprocessors. Memory system design is important because it largely determines a computer's sustained performance. His work emphasizes quantitative analysis of system-level performance.

Hill has made contributions to parallel computer design (e.g., memory consistency models and cache coherence), uniprocessor system design (e.g., caches and translation buffers), computer simulation (e.g., caches, parallel systems, and out-of-order processors), and software (e.g., page tables and cache-conscious optimizations for databases and pointer-based codes). He, for example, is the inventor of the widely-used 3C model of cache behavior (compulsory, capacity, and conflict misses).

Hill's current research is mostly part of the Wisconsin Multifacet Project that seeks to improve the multiprocessor servers that form the computational infrastructure for Internet web servers, databases, and other demanding applications. Work focuses on using the transistor bounty provided by Moore's Law to improve multiprocessor performance, cost, and fault tolerance, while also making these systems easier to design and program.

Hill is an ACM Fellow (2004) for contributions to memory consistency models and memory system design and a Fellow of the IEEE (2000) for contributions to cache memory design and analysis. He co-won the best paper award in VLDB 2001, was named a Wisconsin Romnes Fellow in 1997, and won an NSF Presidential Young Investigator award in 1989. He is a Director of ACM SIGARCH, co-edited Readings in Computer Architecture in 2000, and is co-inventor of 26 United States Patents (several co-issued in the European Union & Japan). He has held visiting positions at Universidad Politecnica de Catalunya (2002-03) and Sun Microsystems (1995-96). Dr. Hill earned a Ph.D. in Computer Science from the University of California - Berkeley in 1987, an M.S. in Computer Science from Berkeley in 1983, and a B.S.E. in Computer Engineering from the University of Michigan - Ann Arbor in 1981.

Mark Moir

Mark Moir received the B.Sc.(Hons.) degree in Computer Science from Victoria University of Wellington, New Zealand in 1988, and the Ph.D. degree in Computer Science from the University of North Carolina at Chapel Hill, USA in 1996. From August 1996 until June 2000, he was an assistant professor in the Department of Computer Science at the University of Pittsburgh. In June 2000, he joined Sun Microsystems Laboratories, where he is now the Principal Investigator of the Scalable Synchronization Research Group. Dr. Moir's main research interests concern practical and theoretical aspects of concurrent, distributed, and real-time computing. His current research focuses on hardware and software mechanisms for achieving non-blocking synchronization in shared-memory multiprocessors. 

Maurice Herlihy

Maurice Herlihy is a professor at Brown University (and currently on sabbatical at Microsoft Research, Cambridge). His research interests center around practical and theoretical aspects of synchronization and concurrency. He is one of the authors of the original 1993 Transactional Memory paper.

Michael Scott

Michael L. Scott is a Professor and past Chair of the Department of Computer Science at the University of Rochester. He received his Ph.D. from the University of Wisconsin-Madison in 1985. His research interests span operating systems, languages, architecture, and tools, with a particular emphasis on parallel and distributed systems. His queue-based spin lock, co-designed with John Mellor Crummey, has been used in several commercial and academic systems. His nonblocking queue, co-designed with Maged Michael, is a standard component of the Java 5 concurrency library. His recent work includes contributions to software transactional memory, and the introduction of "dual data structures", which extend nonblocking semantics to operations that must wait for an invariant. The second edition of _Programming_Language_Pragmatics_, his widely used text on programming language design and implementation, will be available in October 2005. In 2001 he received the University of Rochester's Robert and Pamela Goergen Award for Distinguished Achievement and Artistry in Undergraduate Teaching.

Nir Shavit

Nir Shavit received an B.A. and M.Sc. from the Technion and a Ph.D. from the Hebrew University, all in Computer Science. He was a Postdoctoral Researcher at IBM Almaden Research Center, Stanford University, and MIT, and a Visiting Professor at MIT. He is on the faculty at Tel-Aviv University and is a Member of Technical Staff at Sun Microsystems Laboratories. He is the recipient of the Israeli Industry Research Prize and the 1993 and co-winner of the ACM/EATCS Godel Prize in Theoretical Computer Science in 2004.

His research interests include hardware and software aspects of Multiprocessor Synchronization, the design and implementation of Concurrent Data-Structures, and the Theoretical Foundations of Asynchronous Computability.

Ravi Rajwar

Ravi Rajwar is with the Intel Microprocessor Technology Labs in Hillsboro, OR. His research interests cover microarchitectures and multiprocessors. He received a PhD in Computer Science from the University of Wisconsin-Madison in 2002.

Seckin Unlu

Seckin Unlu is an Intel Fellow, Software and Solutions Group and director of Systems Performance. Since 1995, he has been responsible for analyzing and improving processor and system performance for mid-range and high-end server and workstation products based on Intel's processors, chipsets and platforms.

Previously, he was a Senior Software Engineer and focused on systems development using several operating systems including iNDX, Xenix MultiServer, Unix SVR4 and Windows NT. Unlu joined Intel in 1982.

Unlu was awarded the Intel Achievement Award in 1997 for jointly developing the Application Solution Center methodology. He also represents Intel on the Transaction Processing Performance Council (TPC), which develops the industry's most prevalent processor benchmarks.

In 1979, Unlu received his master's degree in Computer Science and his bachelor's degree in Electrical Engineering from the Middle East Technical University (METU) in Ankara, Turkey. Prior to joining Intel, he continued post-graduate studies on database technologies, while working as the Senior System Analyst at the METU Computer Center from 1979 to 1982.

Unlu holds a patent for mutual exclusion for computer systems.

Suresh Jagannathan

Suresh Jagannathan is an Associate Professor of Computer Science at Purdue University. Prior to joining Purdue, he was a Senior Director at Storage Networks, and a Senior Research Scientist at the NEC Research Institute. His interests are in programming languages and their implementation, distributed algorithms, and storage infrastructure. He received his MS and Ph.d from MIT.

Tim Harris

Tim Harris is a Researcher at Microsoft Research Cambridge where he works on concurrent algorithms and new abstractions for concurrent programming. Previously he was a lecturer in the University of Cambridge Computer Laboratory where he gained his BA and PhD degrees. He is a co-author of the undergraduate text book "Operating Systems" published by Pearson and is a Teaching Fellow at Churchill College, Cambridge, UK.

His research information can be obtained from http://research.microsoft.com/~tharris

M Satyanarayan

Professor Satyanarayanan is an experimental computer scientist who has pioneered research in mobile and pervasive computing. One outcome is the Coda File System, which supports mobility in low-bandwidth and intermittent wireless networks through disconnected and bandwidth-adaptive operation. Key ideas from Coda have been incorporated by Microsoft into the IntelliMirror component of Windows 2000 and the Cached Exchange Mode of Outlook 2003. Another outcome is Odyssey, a set of open-source operating system extensions that enable mobile applications to adapt to variation in critical resources such as network bandwidth and energy. Coda and Odyssey are building blocks in Project Aura, a research initiative at Carnegie Mellon to explore distraction-free ubiquitous computing. His most recent work involves Intenet Suspend/Resume, a hands-free approach to mobile computing that layers virtual machine state on a distributed file system. Early in his career, he was a principal architect and implementor of the Andrew File System (AFS). AFS was commercialized by IBM, is in widespread use today as OpenAFS, and has heavily influenced the NFS v4 network file system protocol standard.

Satyanarayanan is the Carnegie Group Professor of Computer Science at Carnegie Mellon University. From May 2001 to May 2004 he served as the founding director of Intel Research Pittsburgh. He received the PhD in Computer Science from Carnegie Mellon, after Bachelor's and Master's degrees from the Indian Institute of Technology, Madras. He is a Fellow of the ACM and the IEEE, and is the founding Editor-in-Chief of IEEE Pervasive Computing.

Todd Mowry

Todd C. Mowry is the director of Intel Research Pittsburgh while on leave from Carnegie Mellon University, where he is an Associate Professor in the Computer Science Department. He received an M.S.E.E. and Ph.D. from Stanford University in 1989 and 1994, respectively. Dr. Mowry's research interests span computer architecture, compilers, operating systems, parallel processing, and database performance. His research to date has focused primarily on developing new techniques for designing computer systems (both hardware and software) such that they can achieve dramatic performance breakthroughs at low cost without placing any additional burden on the programmer. In particular, the goal of the Profet project was to automatically tolerate the ever-increasing relative latencies of accessing and communicating data (via DRAM, disks, and networks) which threaten to nullify any other improvements in processing efficiency, and the goal of the Stampede project was to automatically extracting thread-level parallelism from important classes of applications where this had not been possible. He received the TR100 Award from MIT's Technology Review magazine and a Sloan Research Fellowship in 1999, and he currently serves on the Editorial Board of ACM Transactions on Computer Systems.

Mark Tuttle

Mark Tuttle is a Principal Member of the Technical Staff at HP Labs working on distributed and concurrent algorithms and fault tolerance. Mark is deeply interested in the fundamental correctness of algorithms, and has worked on models, proof systems, and verification tools for many problems including concurrent data structures, security protocols, database systems, and hardware algorithms (including the checking of cache coherence protocols for HP servers). Mark is also interested in the design of fault-tolerant distributed algorithms. His most recent work concerns recommendation systems in the face of malicious or colluding users, with applications to electronic commerce and web search.