Shubu Mukherjee Distinguished Engineer Cavium Networks Marlborough, MA Email: shubumukherjee001 at gmail dot com LinkedIn page Adjunct Faculty, Indian Institute of Technology, Kanpur IEEE Fellow, Class of 2009 ACM Fellow, Class of 2011

Currently, Shubu Mukherjee is involved in architecting Cavium's next network processor.

In the past, Shubu Mukherjee was a Principal Engineer and Director of Intel's SPEARS Group (Simulation and Pathfinding of Efficient and Reliable Systems). The SPEARS Group was responsible for spearheading architectural change and innovation in the delivery of enterprise processors and chipsets by building and supporting simulation and analytical models of performance, power, and reliability. Shubu has taken 5 innovations in large-scale system monitoring, soft error tolerant microarchitectures, performance simulation, parallel simulation, and on-chip interconnect design from conception to implementation. These innovations have resulted in 100s of millions of dollars in increased revenue for Intel and Compaq, reduced internal costs by 10s of millions of dollars, influenced over a dozen products, and improved customer goodwill significantly.

In 2009, Shubu won the Maurice-Wilkes award for outstanding contributions to computer architecture. This is the highest award given to a mid-career architect. Prior winners include Dirk Meyer (CEO AMD), Bill Dally (Chief Scientist Nvidia), Steve Scott (CTO Cray), and Anant Agarwal (Prof MIT and Founder of Several Companies). Shubu is also a Fellow of IEEE and ACM. He was the General Chair of 2004 ASPLOS and will be the Program Chair for 2011 HPCA conferences. He wrote the seminal book on "Architecture Design for Soft Errors," which has been highly acclaimed by Microprocessor Report as well as researchers and practitioners. Shubu holds 25 patents and has 23 patents pending. He has written over 50 technical papers in top architecture conferences and journals.

Prior to joining Intel, Shubu worked for Digital Equipment Corporation for 10 days and Compaq Computer Corporation for 3 years. His current interests include innovation confluencing, computer architecture, and fault tolerant architectures.

Maurice Wilkes Award in 2009 “for outstanding contributions to modeling and design of soft-error tolerant microarchitectures." Click here for the 2009 Maurice Wilkes Award Press Release

IEEE Fellow, Class of 2009, for contributions to modeling of and protection against radiation-induced soft errors. Awarded to 0.1% of the total IEEE voting body each year.

ACM Fellow, Class of 2011, for contributions to modeling and design of high-performance and soft-error tolerant microarchitectures. Click here for 2011 ACM Fellow Press Release

DEG Achievement Award for large-scale system monitoring, 2009

IEEE Top Picks Awards, 2003 & 2004 for two soft error modeling & architecture papers

Five Intel Divisional Recognition Awards for various technology development around soft errors, 2002 – 2009

Customer Advocacy Award from Compaq CEO Michael Capellas, September 2000. For solving a Circuit City customer's problem having trouble with her Compaq computer.

Ph.d., Computer Science, University of Wisconsin-Madison, May 1998. Advisor Prof. Mark D. Hill. "Design and Evaluation of Network Interfaces for System Area Networks."

MS, Computer Science, University of Wisconsin-Madison, Dec. 1993.

B.Tech., Computer Science and Engineering, Indian Institute of Technology, Kanpur, May 1991.

MIT Sloan School Courses, 2004 – 2009: "Building, Leading, and Sustaining the Innovative Organization," "Strategic Marketing for the Technical Executive," and "Developing & Managing a Successful Technology and Product Strategy."

Intel Course, "Strategy and Action (taught by Prof. Robert Burgelman from Stanford University)"

Cavium Networks, 2010 - present. Architecting Cavium's next network processor.

Intel Corporation, 2001 - 2010. Position: Director & Principal Engineer. Key projects include innovation confluencing in Xeon performance, Xeon reliability, large-scale system monitoring, soft error modeling and tolerant microarchitecture, performance simulation, and parallel simulation.

Compaq Computer Corporation, 1998 - 2001. Various Hardware Engineer Positions. Projects include 21364 on-chip network architecture design, performance simulation, and Redundant Multithreading to detet soft errors.

Chief Executive Officer, KurtaHouse.Com. This was a tiny web-based startup selling Indian's men's clothes (kurtas). Ran at a profit marging of 60-80%.

Click here for Errata

Published by Elsevier, Inc in February 2008. Captures different aspects of the science and engineering around soft errors. Available from amazon.com & other online etailers.

Comments on the book:

Max Baron, Microprocessor Report Book Review, May 27 2008, “Dr. Shubu Mukherjee's book is a welcome surprise: books by architecture leaders in major companies are few and far between. Written from the viewpoint of a working engineer, the book describes sources of soft errors and solutions involving device, logic, and architecture design to reduce the effects of soft errors."

Ishwar Parulkar, Sun Microsystem Distinguished Engineer, "As an architect dealing with practical issues related to soft errors in enterprise class servers, I have always wished for a book that addressed this topic comprehensively. This book fills a critical void in digital design literature and should be mandatory reading for every silicon architect and designer."

Tom Bissett, Lead System Architect, Marathon Technologies Corporation: "Dr. Mukherjee has crafted a highly readable book out of a complex topic. In a limited space, Dr. Mukherjee has done a remarkable job of describing the error sources, categorizing the solution space, and highlighting the attributes of the commercially available systems."

General Chair of 11th Annual International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2004

Program Chair of 17th Annual International Symposium on High-Performance Computer Architecture (HPCA), 2011.

Adjunct faculty of the Indian Institute of Technology, Kanpur, 2009 – Present.

Editorial Board member for IEEE Micro, IEEE Computer Architecture Letters, and IEEE Transactions of Dependable and Secure Computing.

Frequent member of National Science Foundation panels that awards multi-million dollar grants to university researchers.

Frequent member of top architecture and fault tolerance program committees, such as ISCA (International Symposium on Computer Architecture), ASPLOS (Architectural Support for Programming Languages and Operating Systems), DSN (Dependable Systems and Networks), and HPCA (High Performance Computer Architecture). Serve in Intel’s IP committee and am a frequent member of the program committees for Intel Microarchitecture and Platform Architecture conferences.

Keynote speaker in Intel Microarchitecture Conference, Boston Area Architecture Workshop, and Symposium on Defects and Fault Tolerance.

1. Steve Raasch, Mike Powell, Arijit Biswas, and Shubhendu S. Mukherjee, “Using General Purpose Hardware to Replace Faulty Core Components,” filed by Intel, 2009.

2. Shubhendu S. Mukherjee, Arijit Biswas, Steven Raasch, and Paul Racunas, “Fingerprint History Buffer,” filed by Intel, 2008.

3. Arijit Biswas, Nirjanjan Soundarajan, and Shubhendu S. Mukherjee, “Quantized AVF Hardware”, filed 2008.

4. Paul Racunas, Kypros Constantinides, Srilatha Manne, and Shubhendu S. Mukherjee, “Fault Screeners,” filed 2006.

5. George Reis, Robert S. Cohn, and Shubhendu S. Mukherjee, “Transient Fault Tolerance via Binary Translation,” accepted for filing by Intel, 2006.

6. Paul Racunas, Moin Qureshi, and Shubhendu S. Mukherjee, “Demand-Based ECC for Cost-Efficient Fault-Tolerant Cache Memories,” filed by Intel in 2006.

7. Shubhendu S. Mukherjee, “Clock Gating the Arbitration Logic in High-Speed Routers,” accepted for filing, Intel, 2005.

8. Paul Racunas, George Chrysos, Matt Mattina, and Shubhendu S. Mukherjee, “Fixed Latency Lockstep Checker,” filed by Intel, 2005.

9. Paul Racunas, Joel Emer, Arijit Biswas, Shubhendu S. Mukherjee, and Steve Raasch, “Micro-Lockstep Checker,” filed by Intel. 2005.

10. Shubhendu S. Mukherjee, “Local Detection of Global Hotspots in a 2D-Torus“, filed by Intel, 2005.

11. Arijit Biswas, Steve Raasch, and Shubhendu S. Mukherjee, "Localized Soft Error Detection and Recovery using modified scan cells," filed by Intel, 2004.

12. Arijit Biswas, Steve Raasch, and Shubhendu S. Mukherjee, "An On-Die Mechanism to Detect a High Soft Error Rate Environ¬ment," filed by Intel, 2004.

13. Wayne Burleson, Mondira Pant, and Shubhendu S. Mukherjee, "Filtering Latch," filed by Intel 2004.

14. Shubhendu S. Mukherjee, "Packet Coalescing in Interconnection Network Routers," filed by Intel in 2004.

15. Shubhendu S. Mukherjee, "Technique to Effectively Invalidate Translation Buffer Entries in a Multiprocessor, filed by Intel, 2004.

16. Shubhendu S. Mukherjee, "Coalescing Coherence Messages in a Shared-Memory Machine," filed 2004.

17. Shubhendu S. Mukherjee, "Accelerating the Performance of Performance Models via a Parallel Lookup Memory (PLM)", filed by Intel , June 2004.

18. Ugonna Echeruo, George Chrysos, John Crawford, and Shubhendu S. Mukherjee, "Technique to Protect a Translation Lookaside Buffer's Virtual Page Number from soft errors in a processor with multiple page sizes", filed by Intel, 2004.

19. Christopher Weaver, Shubhendu S. Mukherjee, Joel Emer, and Steven K. Reinhardt, "The Post-commit Error Tracking (PET) Buffer: A Technique to Reduce False Error Detection in Microprocessor by Tracking Dynamically Dead Instructions," filed in Intel, 2004.

20. Shubhendu S. Mukherjee, "Lazy Save and Restore (LSR): A Technique to Quickly Save and Restore the Register File on a Con¬text Switch," filed by Intel, 2004.

21. Steven K. Reinhardt, Shubhendu S. Mukherjee, Joel Emer, and Christopher Weaver, "Buffering Unchecked Stores for Fault Detection in RMT Systems using Speculative Memory Support," filed 2003.

22. Shubhendu S. Mukherjee, "Load Value Queue Input Replication In A Simultaneous And Redundantly Threaded Processor," sub¬mitted to patent office, April, 2001.

23. Shubhendu S. Mukherjee and Steven K. Reinhardt, "Simultaneous And Redundantly Threaded Processor Branch Outcome Queue," submitted to patent office, April, 2001.

24. Steven K. Reinhardt and Shubhendu S. Mukherjee, “Fault Detection Using Redundant Virtual Machines,” US Patent 7,587,663, issued Sep. 8, 2009, filed May 22, 2006, assignee Intel Corporation (Santa Clara, CA).

25. Shubhendu S. Mukherjee, "Vectoring process-kill errors to an application program," US Patent 7,373,558, issued May 13, 2008, filed September 23, 2004, assignee Intel Corporation (Santa Clara, CA).

26. Shubhendu S. Mukherjee & Robert Cohn, "Fault free store data path for software implementation of redundant multithreading environments,” US Patent 7,581,152, issued Aug. 25, 2009, filed Dec. 22, 2004, assignee Intel Corporation (Santa Clara).

27. Shubhendu S. Mukherjee, "Optimally Push I/O Data into a Processor's Cache," US Patent 7,574,568, issued Aug. 11th, 2009, filed December 6, 2004, assignee Intel Corporation (Santa Clara).

28. Shubhendu S. Mukherjee, Joel Emer, Steven K. Reinhardt, Mike Smith, and Christopher Weaver, "Method and Apparatus for Reducing False Error Detection in a Microprocessor,” US Patent 7,555,703, issued June 30, 2009, filed June 17, 2004, assignee Intel Corporation (Santa Clara).

29. Shubhendu S. Mukherjee, Joel Emer, Steven K. Reinhardt, Christopher Weaver, and Michael J. Smith, "Method and apparatus for reducing false error detection in a redundant multi-threaded system,” US Patent 7,543,221, issued June 2, 2009, filed Sep¬tember 22, 2004, assignee Intel Corporation (Santa Clara).

30. Wayne Burleson, Shubhendu S. Mukherjee, Vinod Ambrose, and Dan Holcombm “Generalized Interlocked CEll,” US Patent 7,529,118, issued May 5, 2009, filed Mar. 28, 2007, assignee Intel (Santa Clara).

31. Sudhanva Gurumurthi, Arijit Biswas, Joel Emer, and Shubhendu S. Mukherjee, "Detecting Errors in Directory Entries," US Patent 7,475,321, issued January 9, 2009, filed December 29, 2004, assignee Intel Corporation (Santa Clara).

32. Shubhendu S. Mukherjee, “Low Power Arbiters in Interconnectin Networks,” US Patent 7,472,299, issued December 30, 2008, filed September 30, 2005, assignee Intel Corporation (Santa Clara).

33. Steven K. Reinhardt, Shubhendu S. Mukherjee, Joel Emer, and Christopher Weaver, "Managing External Memory Updates for Fault Detection in Redundant Multithreading Systems using Speculative Memory Support," US Patent 7,444,497, issued Octo¬ber 28, 2008, filed December 30, 2003, assignee Intel Corporation (Santa Clara).

34. Joel Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt, and Christopher Weaver, "Reducing false error detection in a micro¬processor by tracking instructions neutral to errors,” US Patent 7,386,756, issued June 10, 2008, filed June 17, 2004, assignee Intel Corporation (Santa Clara).

35. Tryggve Fossum, Yaron Shragai, Ugonna Echeruo, and Shubhendu S. Mukherjee, "Converting Merge Buffer System-Kill Errors to Process-Kill Errors," US Patent 7,380,169, issued May 27, 2008, filed Sep. 27, 2004, assignee Intel Corporation (Santa Clara).

36. Steven K. Reinhardt, Shubhendu S. Mukherjee, and Joel Emer, "Hardware recovery in a multithreaded architecture," US Patent 7,373,548, issued May 13, 2008, filed August 29, 2003, assignee Intel Corporation (Santa Clara, CA).

37. Tryggve Fossum, Yaron Shragai, and Shubhendu S. Mukherjee, "Method for handling errors," US Patent 7,370,231, issued May 6, 2008, filed December 14, 2004, assignee Intel Corporation (Santa Clara, CA).

38. Shubhendu S. Mukherjee, Joel Emer, Steven K. Reinhardt, and Christopher Weaver, "Implementing check instructions in each thread within a redundant multithreading environment," US Patent 7,353,365, issued April 1, 2008, filed September 29, 2004, assignee Intel Corporation (Santa Clara, CA).

39. Shubhendu S. Mukherjee, Steven K. Reinhardt, and Joel Emer, "Periodic Checkpointing in a redundantly multi-threaded archi¬tecture," US Patent 7,308,607, issued December 11, 2007, filed August 29, 2003, assignee Intel Corporation (Santa Clara, CA).

40. Shubhendu S. Mukherjee, Steven K. Reinhardt, and Joel Emer, "Incremental Checkpointing in a multi-threaded architecture," US Patent 7,243,262, issued July 10, 2007, filed August 29, 2003, assignee Intel Corporation (Santa Clara, CA).

41. Shubhendu S. Mukherjee, Richard Kessler, Steve Lang, and David Webb, "Priority Rules for Reducing Network Message Rout¬ing Latency," US Patent 6,961,781, issued Feb. 8th, 2005, filed April 19, 2001, assignee Hewlett-Packard Development Com¬pany, L.P. (Houston, TX). .

42. Shubhendu S. Mukherjee and Steven K. Reinhardt, "Simultaneous and redundantly threaded processor store instruction compar¬ator," US Patent 6,854,075, issued Nov. 1st, 2005, filed August 31st 2000, assignee Hewlett-Packard Development Company, L.P. (Houston, TX).

43. Shubhendu S. Mukherjee, "Cycle Count Replication In A Simultaneous And Redundantly Threaded Processor," United States Patent 6,854,051, issued Feb. 8, 2005, filed 19, 2001, assignee Hewlett-Packard Development Company, L.P. (Houston, TX).

44. Shubhendu S. Mukherjee, "Simultaneous and redundantly threaded processor uncached load address comparator and data value replication circuit," United States Patent 6,823,473, issued Nov. 23rd, 2004, assignee Hewlett-Packard Development Company, L.P. (Houston, TX), filed April 19, 2001.

45. Shubhendu S. Mukherjee and Steven K. Reinhardt, "Input Replicator For Interrupts In A Simultaneous And Redundantly Threaded Processor," United States Patent 6,792,525, issued Sep. 14, 2004, assignee Hewlett-Packard Development Company, L.P. (Houston, TX), filed April 19, 2001.

46. Shubhendu S. Mukherjee, "Slack Fetch to Improve Performance of a Simultaneous and Redundantly Threaded Processor," United States Patent 6,757,811, issued June 29, 2004, assignee Hewlett-Packard Development Company, L.P. (Houston, TX), filed May 30, 2000.

47. Shubhendu S. Mukherjee and Steven K. Reinhardt, "Active Load Address Buffer In A Simultaneous And Redundantly Threaded Processor," United States Patent 6,598,122, issued July 22, 2003, assignee Hewlett-Packard Development Company, L.P. (Hous¬ton, TX) filed April 19, 2001.

48. David A. Wood, Steven K. Reinhardt, Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, and Robert W. Pfile, "Cachable interface control registers for high speed data transfer," United States Patent 5,951,657 issued September 14, 1999. assignee Wisconsin Alumni Research Foundation (WARF), filed June 9, 1997.

1. Norbert, Seifert, Vinod Ambrose, Balkaran Gill, Randy Allmon, Quan Shi, Charlie Recchia, Shubu Mukherjee, Nevine Nassif, Jon Krause, Jeffrey Pickholtz, and Anupama Balasubramanian, “On the radiation-induced soft error performance of hardened sequential elements in an advanced bulk CMOS technologies,” submitted for publication.

2. Arijit Biswas, Charles Recchia, Shubhendu S. Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Mike Plaster, and Norbert Seifert, “Explaining Cache SER Anomaly Using Relative DUE AVF Measurement,” HPCA 2010.

3. Mike Powell, Arijit Biswas, Shantanu Gupta, and Shubhendu S. Mukherjee, “Architectural Core Salvaging for Hard Error Toler¬ance,” ISCA 2009.

4. Shubu Mukherjee, “Computer Glitches from Radiaion: A Problem With Multiple Solutions,” Microprocessor Report, May 19, 2008.

5. Michael Powell, Arijit Biswas, Joel Emer, Shubhendu S. Mukherjee, Basit Sheikh, and Shrirang Yardi, “Common Activity-based Modeling for Power Analysis at Design and Runtime,” High Performance Computer Architecture (HPCA), Feb. 2009.

6. Arijit Biswas, Niranjan Soundararajan, and Shubhendu S. Mukherjee, “Analysis and Evaluation of Quantized AVF,” SELSE 2009.

7. Shubhendu S. Mukherjee, Carl Beckmann, Joel Emer, Sailashri Parthasarathy, Brian Slechta, Michael Adler, Aamer Jaleel, and Krishna Rangan, “Speeding up Performance Models Using Modular Design,” Intel Platform Architecture Conference (IPAC), Nov 2007 and Intel Test, and Technology Conference (DTTC), 2008.

8. Arijit Biswas, Paul Racunas, Joel Emer, and Shubhendu S. Mukherjee, “Computing Accurate AVFs using ACE Analysis on Per¬formance Models: A Rebuttal,” Computer Architecture Letters (CAL), December 2007.

9. Antonio Gonzalez, Scott Mahlke, Shubu Mukherjee, Derek Chou, and Joshua Li, “Reliability: Fallacy or Fortune,” IEEE Micro, Dec. 2007.

10. Arijit Biswas and Shubhendu S. Mukherjee, “The Curse of the Constant AVF,” Intel Confidential, Intel Design, Test, and Tech¬nology Conference (DTTC), March 2007.

11. V. Ambrose, W. Burleson, D. Holcomb, S. Mukherjee, J. Pickhotlz, “A Fast, Accurate Method for Simulating SER in Large Combinational Circuits”, Intel Design & Test Technology Conf. (DTTC), March 2007.

12. Paul Racunas, Srilatha Manne, Kypros Constantinides, & Shubhendu S. Mukherjee, “Probabilistic Fault Screening,” High Per¬formance Computer Architecture, Feb. 2007.

13. George Reis, David August, Robert Cohn, and Shubhendu S. Mukherjee, “Configurable Fault Detection via Dynamic Binary Translation,” WAR Workshop, associated with MICRO, Dec. 2006.

14. George Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David August, and Shubhendu S. Mukherjee, “Software-Con¬trolled Fault Tolerance,” ACM Transactions on Architecture and Code Optimizations, Dec. 2005.

15. Arijit Biswas, John Crawford, Steve Raasch, Shubhendu S. Mukherjee, and Nelson Tam, “SEMA: Soft Error Monitoring Agent,” Intel Internal Conference, DTTC, August 2005.

16. Arijit Biswas, Paul Racunas, Raz Cheveresan, Joel Emer, Shubhendu S. Mukherjee, and Ram Rangan, “Computing the Archi¬tectural Vulnerability Factors for Address-Based Structures,” International Symposium on Computer Architecture (ISCA), Mad¬ison, Wisconsin, USA, June 2005.

17. George Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David August, and Shubhendu S. Mukherjee, “Design and Eval¬uation of Hybrid Fault-Detection Systems,” International Symposium on Computer Architecture (ISCA), Madison, Wisconsin, USA, June 2005.

18. Shubhendu S. Mukherjee, Joel Emer, and Steven K. Reinhardt, “The Soft Error Problem: An Architectural Perspective,” 11th International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2005.

19. Christopher Weaver, Joel Emer, Shubhendu S. Mukherjee, and Steven K. Reinhardt, “Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor,” IEEE Micro Top Picks, Nov/Dec. 2004.

20. Christopher Weaver, Joel Emer, Shubhendu S. Mukherjee, and Steven K. Reinhardt, "Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor," International Symposium on Computer Architecture (ISCA), Germany, June 2004.

21. Shubhendu S. Mukherjee, Joel Emer, Tryggve Fossum, and Steven K. Reinhardt, "Cache Scrubbing in Microprocessors: Myth or Necessity?" 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), March 3-5 2004, Papeete, French Polynesia.

22. Shubu Mukherjee, "Fault Tolerance Techniques for COTS Hardware," Position Paper for Panel in the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), March 3-5 2004, Papeete, French Polynesia.

23. Mithuna Thottethodi, Alvin Lebeck, and Shubhendu S. Mukherjee, "Exploiting Global Knowledge to Achieve Self-Tuned Con¬gestion Control for k-ary n-cube Networks," IEEE Transactions on Parallel and Distributed Systems, Vol. 15, No. 2, February 2004.

24. Shubhendu S. Mukherjee, Christoper Weaver, Joel Emer, Steven K. Reinhardt, and Todd Austin, "Measuring Architectural Vul¬nerability Factors," Top picks of 2003 in IEEE Micro, Nov/Dec2003.

25. Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steven K. Reinhardt, and Todd Austin, "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor," to appear in the 36th Annual Inter¬national Symposium on Microarchitecture (MICRO), December 2003.

26. Shubhendu S. Mukherjee, "An Architectural Perspective on Soft Errors from Cosmic Radiation," International Federation for Information Processing (IFIP), WG 10.4 - Dependable Computing and Fault Tolerance, June 25-29, 2003.

27. Mithuna Thottethodi, Alvin Lebeck, and Shubhendu S. Mukherjee, "High-Performance Routing Algorithms for Virtual Cut-Through Networks," International Parallel and Distribtued Processing Symposium (IPDPS), April, 2003.

28. Shubhendu S. Mukherjee, Federico Silla, Peter Bannon, Joel Emer, Steve Lang, and David Webb, "A Comparative Study of Arbitration Algorithms for the Alpha 21364 Pipelined Router," Tenth Annual International Symposium on Architectural Support for Programming Languages and Operating Systems, San Jose, October 2002. Also, appears in the First Intel Microarchiteture Conference, Oregon, May 2002.

29. Shubhendu S. Mukherjee, Michael Kontz, and Steven K. Reinhardt, "Detailed Design and Evaluation of Redundant Multithread¬ing Alternatives," 29th Annual International Symposium on Computer Architecture (ISCA), 2002.

30. Shubhendu S. Mukherjee, "New Challenges in Benchmarking Future Processors," Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads, associated with HPCA-8, February 2002.

31. Shubhendu S. Mukherjee, Sarita Adve, Todd Austin, Joel Emer, and Peter Magnusson, "Guest Editors' Introduction: Perfor¬mance Simulation Tools," IEEE Computer, February 2002.

32. Joel Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan Binkert, Roger Espasa, and Toni Juan, "Asim: A Performance Model Framework," IEEE Computer, February 2002.

33. Shubhendu S. Mukherjee, Peter Bannon, Steve Lang, and David Webb, "The Alpha 21364 Network Architecture," Hot Intercon¬nects IX, August, 2001. Also, appears in IEEE Micro, January/February 2002.

34. Pritpal Ahuja, Joel Emer, Artur Klauser, and Shubhendu S. Mukherjee, "Performance Potential of Effective Address Prediction," Accepted for publiation in the Workshop on Memory Performance Issues, held in conjunction with the 28th Annual Interna¬tional Symposium on Computer Architecture (ISCA), July, 2001.

35. Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, and Andre Seznec, "Boosting SMT Performance by Speculation Control," International Parallel and Distribtued Processing Symposium (IPDPS), April, 2001.

36. Mithuna Thottethodi, Alvin Lebeck, and Shubhendu S. Mukherjee, "Self-Tuned Congestion Control for Multiprocessor Net¬works," Accepted for publication in the International Symposium on High-Performance Computer Architecture (HPCA), Jan. 2001. An extended version of this paper appears as a technical report: Mithuna Thottethodi, Alvin Lebeck, and Shubhendu S. Mukherjee, "Self-Tuned Congestion Control for Multiprocessor Networks," Technical Report CS-2000-15, Duke University, Nov. 2000. Also, a version of this has been accepted for publication in the IEEE Journal of Transactions of Parallel and Distrib¬uted Computing.

37. Shubhendu S. Mukherjee, Steven K. Reinhardt, Babak Falsafi, Mike Litzkow, Steve Huss-Lederman, Mark D. Hill, James R. Larus, and David A. Wood, "Wisconsin Wind Tunnel II: A Fast and Portable Parallel-Architecture Simulator," IEEE Concur¬rency, Oct, 2000. A prior version of this paper appeared in the Workshop on Performance Analysis and Its Impact on Design (PAID), June 1997 (associated with ISCA).

38. Steven K. Reinhardt and Shubhendu S. Mukherjee, "Transient Fault Detection via Simultaneous Multithreading," in Proceedings of the 27th International Symposium on Computer Architecture, June 2000.

39. Andrew Chien, Mark D. Hill, Shubhendu S. Mukherjee, "Guest Editors' Introduction: Design Challenges for High-Performance Network Interfaces," IEEE Computer, November, 1998.

40. Shubhendu S. Mukherjee and Mark D. Hill, "A Case for Making Network Interfaces Less Peripheral," IEEE Computer, October, 1998. A talk-only version of this paper appears in Hot Interconnects V, August, 1997.

41. Shubhendu S. Mukherjee and Mark D. Hill, "Using Prediction to Accelerate Coherence Protocols," Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA), Barcelona, Spain, June 1998.

42. Shubhendu S. Mukherjee and Mark D. Hill, "The Impact of Data Transfer and Buffering Alternatives on Network Interface Design," Fourth International Symposium on High-Performance Computer Architecture (HPCA), Feb. 1998.

43. Shubhendu S. Mukherjee, "What Should Graduate Students Know Before Joining a Large Computer Architecture Project?" Computer Architecture News (CAN), March 1997.

44. Shubhendu S. Mukherjee and Mark D. Hill, "A Survey of User-Level Network Interfaces for System Area Networks," Technical Report #1340, Computer Sciences Department, University of Wisconsin-Madison, February 1997.

45. Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, and David A. Wood, "Coherent Network Interfaces for Fine-Grain Com¬munication," Proceedings of the 23rd Annual International Symposium on Computer Architecture (ISCA), May 1996.

46. Ioannis Schoinas, Babak Falsafi, Mark D. Hill, James R. Larus, Christopher Lukas, Shubhendu S. Mukherjee, Steven K. Rein¬hardt, Eric Schnarr, and David A. Wood, "Implementing Fine-Grain Distributed Shared Memory on Commodity SMP Worksta¬tions," Technical Report CS-TR-96-1307, Computer Sciences Department, University of Wisconsin-Madison, March 1996.

47. Shubhendu S. Mukherjee, Shamik D. Sharma, Mark D. Hill, James R. Larus, Anne Rogers,and Joel Saltz, "Efficient Support for Irregular Applications on Distributed-Memory Machines," Proceedings of the Fifth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), July 1995.

48. Shubhendu S. Mukherjee, Alan Kagi, and Douglas Burger, "A Programming Tutorial for the Wisconsin Wind Tunnel," Revised January 1995.

49. Shubhendu S. Mukherjee and Mark D. Hill, "An Evaluation of Directory Protocols for Medium-Scale Shared-Memory Multi¬processors," Proceedings of the International Conference on Supercomputing (ICS), Manchester, England, July 1994.

50. David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, and Steven K. Reinhardt, "Mechanisms for Cooperative Shared Memory," Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA), May 1993. Also appears in Computer Measurement Group (CMG) Transactions, Spring 1994.

51. Paul R. Wilson, Sheetal V. Kakkad, and Shubhendu S. Mukherjee, "Anomalies and Adaptation in the Analysis and Development of Prepaging Policies," Journal of Systems and Software, 27:147-153, 1994.