Shubu Mukherjee

Shubu Mukherjee is a Principal Engineer and Director of Intel's SPEARS Group (Simulation and Pathfinding of Efficient and Reliable Systems). The SPEARS Group is responsible for spearheading architectural change and innovation in the delivery of enterprise processors and chipsets by building and supporting simulation and analytical models of performance, power, and reliability. Dr. Mukherjee is widely recognized both within and outside Intel as one of the experts on architecture design for soft errors. He has made pioneering contributions towards architectural vulnerability modeling for soft errors, Redundant Multithreading (RMT) techniques, the design of Intel's System Environment Monitoring Agent (SEMA) that runs on 100s of 1000s of processor cores within Intel, creation of performance modeling infrastructures called Cameroon (jointly with a team of Intel engineers) and Asim (jointly with Dr. Joel Emer), design of the Alpha 21364 interconnection network, and the creation of the first shared memory prediction scheme.

Prior to joining Intel, Dr. Mukherjee worked in Compaq for 3 years and Digital Equipment Corporation for 10 days. Dr. Mukherjee received his B.Tech. from the Indian Institute of Technology, Kanpur, where he serves as an adjunct faculty now. He got his M.S. and PhD from the University of Wisconsin-Madison. He is a Fellow of IEEE. He won the 2009 Maurice-Wilkes award for his work on soft errors. He was the General Chair of ASPLOS (Architectural Support for Programming Languages and Operating Systems), 2004. He has co-authored over 50 external papers. He holds 25 patents and has filed another 26 more in Intel. Dr. Mukherjee's book titled, "Architecture Design for Soft Errors" appeared in the market in February 2008. Dr. Mukherjee serves in the Editorial Board of IEEE Computer Architecture Letters (CAL), IEEE Micro, as an Associate Editor of IEEE Transactions of Secure and Dependable Computing (TDSC), in National Science Foundation (NSF) panels, in numerous technical program committees, in Intel Corporation's patent committee, and in the Board of Trustees of Merrimack Repertory Theatre.

His current interests include innovation management, online test, large scale system monitoring, reconfigurable computing, and high performance computing.

Index:-

Education:-

Publications:- (Click on the button for electronic copy of the publication)

Explaining Cache SER Anomaly Using Relative DUE AVF Measurement Arijit Biswas, Charles Recchia, Shubhendu S. Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Mike Plaster, and Norbert Seifert, HPCA 2010.

2009:

Architectural Core Salvaging for Hard Error Tolerance Mike Powell, Arijit Biswas, Shantanu Gupta, Shubhendu S. Mukherjee, ISCA 2009

Quantized AVF Arijit Biswas, Niranajan Soundarajan, Shubhendu S. Mukherjee, and Sudhanva Gurumurthi, SELSE 2009

Common Activity-based Modeling for Power Analysis at Runtime Mike Powell, Arijit Biswas, Joel Emer, Shubhendu S. Mukherjee, Basit Sheikh, and Shrirang Yardi, HPCA 2009

2008:

Book: "Architecture Design for Soft Errors" Shubu Mukherjee, publisher Morgan-Kaufmann, Feb. 2008
ERRATA
Review by Microprocessor Report
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Computer Glitches from Radiation: A Problem with Multiple Solutions Shubu Mukherjee, Microprocessor Report, May 19, 2008

2007:

Computing Accurate AVFs Using ACE Analysis on Performance Models: A Rebuttal Arijit Biswas, Paul Racunas, Joel Emer, and Shubhendu S. Mukherjee, Computer Architecture Letters (CAL), Dec 2007.

Reliability: Fallacy or Reality?` Antonio Gonzalez, Scott Mahlke, Shubu Mukherjee, Resit Sendag, Derek Chiou, and Joshua J. Yi, IEEE Micro, Nov/Dec 2007.

Perturbation-Based Fault Screening Paul Racunas, Kypros Constantinides, Srilatha Manne, and Shubhendu S. Mukherjee, HPCA 2007

2006:

Configurable Transient Fault Detection via Binary Translation George Reis, Jonathan Chang, David August, Robert Cohn, and Shubhendu S. Mukherjee, WAR-2, 2006

2005:

Computing the Architectural Vunerability Factor for Address-Based Structures Arijit Biswas, Paul Racunas, Raz Cheveresan, Joel Emer, Shubhendu S. Mukherjee, and Ram Rangan, June, ISCA 2005

Design and Evaluation of Hybrid Fault Detection Systems George Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David August, and Shubhendu S. Mukherjee, June, ISCA 2005.

The Soft Error Problem: an Architectural Perspective, Shubhendu S. Mukherjee, Joel Emer, and Steven K. Reinhardt, HPCA Feb. 2005.

2004:

Techniques to Reduce the Soft Errors Rate in a High-Performance Microprocessor, Christopher Weaver, Joel Emer, Shubhendu S. Mukherjee, and Steven K. Reinhardt, ISCA, Munich, Germany, June 2004 Click here for the talk. A shorter version of this paper appears in IEEE Micro Nov/Dec, 2004 issue on Top Picks of Computer Architecture papers.

Cache Scrubbing in Microprocessors: Myth or Necessity? Shubhendu S. Mukherjee, Joel Emer, Tryggve Fossum, and Steven K. Reinhardt, 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), March 3 - 5, 2004, Papeete, French Polynesia. Click here for the talk.

Exploiting Global Knowledge to Achieve Self-Tuned Congestion Control for k-ary n-cube Networks, Mithuna Thottethodi, Alvin Lebeck, and Shubhendu S. Mukherjee IEEE Transactions on Parallel and Distributed Systems, Vol. 15, No. 2, February 2004.

2003:

A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor, Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steve Reinhardt, and Todd Austin, MICRO, December 2003, Annaheim, California. Click here for the talk. A shorter version of this paper appears in IEEE Micro Nov/Dec 2003 issue on Top Picks of Computer Architecture papers.

BLAM: A High-Performance Routing Algorithm for Virtual Cut-Through Networks , Mithuna Thottethodi, Alvin Lebeck, and Shubhendu S. Mukherjee International Parallel and Distributed Symposium, April 2003, Nice, France.

2002:

A Comparative Study of Arbitration Algorithms for the Alpha 21364 Router Pipeline , Shubhendu S. Mukherjee, Federico Silla, Peter Bannon, Joel Emer, Steve Lang, and David Webb. Tenth Annual International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, October 2002. Also, in First Intel Microarchitecture Conference, May 2002. Click here for the talk.

Detailed Design and Evaluation of Redundant Multithreading Alternatives Shubhendu S. Mukherjee, Michael Kontz, and Steven K. Reinhardt. 29th Annual International Symposium on Computer Architecture (ISCA), May 2002.

Guest Editors' Introduction: Performance Simulation Tools Shubhendu S. Mukherjee, Sarita V. Adve, Todd Austin, Joel Emer, and Peter Magnusson, IEEE Computer, Feburary 2002.

Please respect the IEEE Copyright notice: "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicity permission of the copyright holder."

Asim: A Performance Model Framework, Joel Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan Binkert, Roger Espasa, and Toni Juan. IEEE Computer, February 2002.

Please respect the IEEE Copyright notice: "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicity permission of the copyright holder."

New Challenges in Benchmarking Future Processors , Shubhendu S. Mukherjee, Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads, associated with HPCA-8, February 2002.

The 21364 Network Architecture , Shubhendu S. Mukherjee, Peter Bannon, Aaron Spink, Steve Lang, and David Webb, IEEE Micro, volume 22, number 1, January/February 2002. Also, appears in Hot Interconnects, Aug. 2001.

Please respect the IEEE Copyright notice: "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicity permission of the copyright holder."

2001:

Performance Potential of Effective Address Prediction , Pritpal Ahuja, Joel Emer, Artur Klauser, and Shubhendu S. Mukherjee, Accepted for publication in the Workshop on Memory Performance Issues, held in conjuction with the 28th Annual International Symposium on Computer Architecture (ISCA), July, 2001.

Boosting SMT Performance by Speculation Control , Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, and Andre Seznec. Accepted for publication in the International Parallel and Distributed Processing Symposium, April, 2001.

Self-Tuned Congestion Control for Multiprocessor Networks. , Mithuna Thottethodi, Alvin Lebeck, and Shubhendu S. Mukherjee, Seventh International Symposium on High-Performance Computer Architecture (HPCA), Jan, 2001.

2000:

Transient Fault Detection via Simultaneous Multithreading , Steven K. Reinhardt and Shubhendu S. Mukherjee, Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA), June, 2000.

1998:

Special Issue on Design Challenges for High-Performance Network Interfaces, Guest Editors - Andrew A. Chien, Mark D. Hill, and Shubhendu S. Mukherjee, Nov. 1998.

Making Network Interfaces Less Peripheral. Shubhendu S. Mukherjee and Mark D. Hill. IEEE Computer, Oct. 1998. Abstract. A talk-only version of this paper appears in Hot Interconnects V, August, 1997. Click here for the slides from the talk. Clip from EE Times.

Using Prediction to Accelerate Coherence Protocols. Shubhendu S. Mukherjee and Mark D. Hill, Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA), Jun. 1998. Abstract.

Design and Evaluation of Network Interfaces for System Area Networks , Shubhendu S. Mukherjee, Ph.D. Thesis, May 1998. Abstract.

The Impact of Data Transfer and Buffering Alternatives on Network Interface Design. Shubhendu S. Mukherjee and Mark D. Hill. Fourth International Symposium on High-Performance Computer Architecture (HPCA), Feb. 1998. Abstract.

1997:

Wisconsin Wind Tunnel II: A Fast and Portable Parallel Architecture Simulator. Shubhendu S. Mukherjee, Steven K. Reinhardt, Babak Falsafi, Mike Litzkow, Steve Huss-Lederman, Mark D. Hill, James R. Larus, and David A. Wood. Workshop on Performance Analysis and its Impact on Design, June 1997 (PAID-97), held in conjunction with ISCA-97.

What Should Graduate Students Know Before Joining a Large Computer Architecture Project? Shubhendu S. Mukherjee, Computer Architecture News (CAN), March 1997. Abstract.

A Survey of User-Level of Network Interfaces for System Area Networks. Shubhendu S. Mukherjee and Mrk D. Hill. Computer Sciences Department, University of Wisconsin-Madison, Technical Report #1340, Feb. 1997. This is a detailed version of the paper titled, "A Case for Making Network Interfaces Less Peripheral." Abstract.

1996:

Coherent Network Interfaces for Fine-Grain Communication. Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, and David A. Wood. 23rd Annual International Symposium on Computer Architecture (ISCA), May 1996. Abstract. Raw Data.

Implementing Fine-Grain Distributed Shared Memory on Commodity SMP Workstations. Ioannis Schoinas, Babak Falsafi, Mark D. Hill, James R. Larus, Christopher Lukas, Shubhendu S. Mukherjee, Steven K. Reinhardt, Eric Schnarr, and David A. Wood. Technical Report, CS-TR-96-1307, University of Wisconsin-Madison, March 19, 1996.

1995:

Efficient Support for Irregular Applications on Distributed-Memory Machines. Shubhendu S. Mukherjee, Shamik D. Sharma, Mark D. Hill, James R. Larus, Anne Rogers, Joel Saltz. Fifth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), July 1995. Abstract.

A Programming Tutorial for the Wisconsin Wind Tunnel. Shubhendu S. Mukherjee, Alan Kagi, and Douglas Burger. (Unpublished manuscript, revised January 1995). Abstract.

1994:

An Evaluation of Directory Protocols for Medium-Scale Shared-Memory Multiprocessors. Shubhendu S. Mukherjee and Mark D. Hill. International Conference on Supercomputing (ICS), Manchester, England, July 1994. Abstract.

Anomalies and Adaptation in the Analysis and Development of Prepaging Policies. Paul R. Wilson, Sheetal V. Kakkad, and Shubhendu S. Mukherjee. Journal of Systems and Software, 27:147-153, 1994. Abstract.

1993:

Mechanisms for Cooperative Shared Memory. David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, Steven K. Reinhardt. 20th Annual International Symposium on Computer Architecture (ISCA), May 1993. Also appears in Computer Measurement Group (CMG) Transactions, Spring 1994. Abstract.

Patents (Submitted & Awarded) :-

Total of 19 issued & 29 more in flight (filed or to be filed)

Old List:-

Shubhendu S. Mukherjee, "Load Value Queue Input Replication In A Simultaneous And Redundantly Threaded Processor," submitted to patent office, April, 2001.

Shubhendu S. Mukherjee, "Uncached Load Address Comparator And Data Value Replication Circuit In A Simultaneous and Redundantly Threaded Processor," submitted to patent office, April, 2001.

Shubhendu S. Mukherjee, "Cycle Count Replication In A Simultaneous And Redundantly Threaded Processor," submitted to patent office, April, 2001.

Shubhendu S. Mukherjee, "Store Instruction Comparator In A Simultaneous And Redundantly Threaded Processor," submitted to patent office, April, 2001.

Shubhendu S. Mukherjee and Steven K. Reinhardt, "Simultaneous And Redundantly Threaded Processor Branch Outcome Queue," submitted to patent office, April, 2001.

Shubhendu S. Mukherjee, Richard Kessler, Steve Lang, and David Webb, "Priority Rules for Reducing Network Message Routing Latency," submitted to patent office, Aug, 2000.

Shubhendu S. Mukherjee and Steven K. Reinhardt, "Input Replicator For Interrupts In A Simultaneous And Redundantly Threaded Processor," United States Patent 6,792,525, issued Sep. 14, 2004, assignee Hewlett-Packard Development Company, L.P. (Houston, TX), filed April 19, 2001.

Shubhendu S. Mukherjee and Steven K. Reinhardt, "Active Load Address Buffer In A Simultaneous And Redundantly Threaded Processor," United States Patent 6,598,122, issued July 22, 2003, assignee Hewlett-Packard Development Company, L.P. (Houston, TX), filed April 19, 2001.

Shubhendu S. Mukherjee, "Slack Fetch to Improve Performance of a Simultaneous and Redundantly Threaded Processor," United States Patent 6,757,811, issued June 29, 2004, assignee Hewlett-Packard Development Company, L.P. (Houston, TX), filed May 30, 2000.

David A. Wood, Steven K. Reinhardt, Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, and Robert W. Pfile, "Cachable interface control registers for high speed data transfer," United States Patent 5,951,657, issued September 14, 1999, assignee Wisconsin Alumni Research Foundation (WARF), filed June 9, 1997.

Public Talks (out of date):-

It's the Interface, Stupid CAC Panel, Shubu Mukherjee, 2002

Redundant Multithreading Shubu Mukherjee, Sep, 2000

Self-Tuned Congestion Control for Multiprocessor Networks Shubu Mukherjee, Sep, 2000

ISCA 2000 Panel. Slow Wires, Hot Chips, and Leaky Transistors: New Challenges in the New Millennium" Moderator: Shubu Mukherjee. Panelists: Bob Colwell, Dirk Grunwald, and Mark Horowitz, Norm Jouppi, Jim Smith, and T.N.Vijaykumar.

Why Short Wires Scale, but Long Wires Don't? Stephen Felix and Shubu Mukherjee, March, 2000

Transient Fault Detection via Simultaneous Multithreading , Shubhendu S. Mukherjee, Jan. 2000.

The Alpha 21364 and 21464 Microprocessors: Continuing the Performance Lead Beyond Y2k , Shubhendu S. Mukherjee, 1999

Using Prediction to Accelerate Coherence Protocols. Shubhendu S. Mukherjee, ISCA, Barcelona, Spain, July, 1998.

The Impact of Data Transfer and Buffering Alternatives on Network Interface Design. Shubhendu S. Mukherjee, HPCA, Las Vegas, Feb, 1998.

Other Talks

Awards:-

• 2009: Maurice Wilkes Award
• 2009: IEEE Fellow
• 2009: DEG Achievement Award
• 2009: ACM Distinguished Engineer
• 2008: Divisional Recognition Award, Intel, 2008
• 2007: Divisional Recognition Award, Intel, 2007
• 2006: Divisional Recognition Award, Intel, 2006
• 2005: Divisional Recognition Award, Intel, 2005
• 2005: ISCA Hall of Fame, 2005
• 2004: Outstanding career award, South Point High School, Mar. 28, 2004
• 2004: Top Picks paper in IEEE Micro
• 2003: IEEE Senior Member
• 2003: Top Picks paper in IEEE Micro
• 2001: Oustanding Achievement Award, Compaq
• 2000: Customer Advocacy Award, Compaq

Professional Activities

• Program Committee Member, Supercomputing 2010
• Program Committee Member, ISCA 2010
• Program Committee Member, DSN 2010
• Co-Chair for Tutorials & Workshops, HPCA 2010
• Program Committee Member, High Performance Computer Architecture (HPCA), 2010
• Program Committee Member, Supercomputing, 2009
• Program Committee Member, IOLTS, 2009
• Program Committee Member, High Performance Computer Architecture (HPCA), 2009.
• Program Committee Member, DATE 2009.
• Program Committee Member, High Performance Computer Architecture (HPCA), 2008.
• Steering Committee Member, BARC 2007.
• Program Committee Member, WAR-2, Workshop associated with MICRO, 2006.
• Member of Editorial Board, IEEE Computer Architecture Letters.
• Steering Committee Member, ASPLOS 2006.
• Program Committee Member, 1st Workshop on Architectural Support for Gigascale Integration, associated with ISCA, June 2006.
• Program Committee Member, 12th Intel Microarchitecture Conference, June 2006.
• Steering Committee Member, BARC 2006.
• Program Committee Member, Architecture for Reliability Workshop in conjunction with MICRO 2005.
• NSF (National Science Foundation) Panel Member for NSF Career awards, 2005.
• Panelist, P=AC2 2005 conference held at IBM T.J.Watson. Panel subject “Reliability Metrics.
• Program Committee Member, Parallel Architecture and Compilation Techniques (PACT), 2005
• Program Committee Member for the 11th International Symposium on High-Performance Computer Architecture (HPCA), 2005.
• Program Committee Member for the IEEE Micro Nov/Dec, 2004 Top Picks Issue.
• General Chair, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2004.
• Program Committee Member, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2004.
• Program Committee Member for the Tenth International Conference on Parallel and Distributed Systems (ICPADS), July 2004.
• Program Committee Member for the Tenth International Symposium on High-Performance Computer Architecture (HPCA), 2004.
• Program Committee Member for the Eleventh Hot Interconnects Symposium, August 2003.
• Program Committee Member, Workshop on Communication Architecture for Clusters, associated with IPDPS, April 2003.
• Program Committee Member for the Workshop on Evaluating and Architecting System Dependability (EASY), October 2002, associated with ASPLOS 2002, San Jose, CA.
• Program Committee Member for the Tenth Hot Interconnects Symposium, August 2002.
• Program Committee Member for the Workshop on Self-Managed and Self-Healing Systems, associated with the International Conference on Supercomputing (ICS), June 2002.
• Panelist for Workshop on Communication Architecture for Clusters, associated with IPDPS, April 15, 2002.
• Program Committee Member for the Eighth International Symposium on High-Performance Computer Architecture (HPCA), 2002.
• Finance Chair for the Eighth International Symposium on High-Performance Computer Architecture (HPCA), Feb, 2002.
• Guest Co-Editor for IEEE Computer Special Issue (Feb, 2002) titled, "Performance Simulation Tools." Jointly with Sarita Adve, Todd Austin, Joel Emer, and Peter Magnusson.
• Session Chair for the Eigth International Symposium on High-Performance Computer Architecture (HPCA), Jan, 2002.
• Program Committee Member for the 2nd International Symposium on Performance Analysis of Systems and Software (ISPASS), Nov, 2001.
• Program Commitee Member for the Workshop on Binary Translation (WBT), associated with PACT, Barcelona, Spain, Sep, 2001.
• Program Committee Member for the Workshop on Evaluating and Architecting System Dependability (EASY), July 1, 2001, associated with ISCA, 2001, Sweden.
• Session Chair for Microarchitecture-I for the Seventh International Symposium on High-Performance Computer Architecture (HPCA), Jan, 2001.
• Program Committee Member for the HPCA-7 Work-in-Progress Session organized by Prof. Jose Duato, 2001.
• Program Committee Member for the Seventh International Symposium on High-Performance Computer Architecture (HPCA), 2001.
• Moderator for the panel, "Slow Wires, Hot Chips, and Leaky Transistors: New Challenges in the New Millennium," at 27th International Symposium on Computer Architecture (ISCA 27), Vancouver, B.C., June 12-14, 2000. Panelists: Dr. Bob Colwell, Prof. Dirk Grunwald, Dr. Norm Jouppi, Prof. Mark Horowitz, Prof. Jim Smith & Prof. T.N.Vijaykumar.
• Program Committee Member for "Workshop on Solving the Memory Wall Problem," to be held in conjunction with the 27th International Symposium on Computer Architecture (ISCA 27), Vancouver, B.C., June 12-14, 2000.
• Guest Co-Editor for IEEE Computer Special Issue (to appear Nov. 1998) titled, "Design Challenges for High-Performance Network Interfaces." Jointly with Andrew Chien and Mark Hill.
• Member, Graduate Advising Committee, Computer Sciences Department, UW-Madison, 9/93 - 8/95
• Society Memberships: ACM (SIGARCH, SIGOPS, SIGMETRICS) and IEEE (Computer Society).
• Prepared answers to teacher's manual for the text book, "A Programmer's View of Computer Architecture", by Jim Goodman and Karen Miller.
• Secretary, Association for Computing Activities (ACA), IIT-Kanpur, 8/90 - 5/91.

Past Life:-