Computer Sciences Dept.

Gurindar S. Sohi

John P. Morgridge Professor
E. David Cronon Professor of Computer Sciences
UW-Madison Computer Architecture Group
Departments of Computer Sciences
and Electrical and Computer Engineering
University of Wisconsin-Madison
2006 Photo of Gurindar S. Sohi by Bob Rashid
By Bob Rashid in 2006
Research Interests
Computer architecture, parallel computing, memory systems, and performance evaluation.

Teaching Interests: Computer organization (CS/ECE 354 and 552), computer architecture (752), and parallel computer architecture (757).

Ph.D.: Electrical and Computer Engineering, University of Illinois, 1985.

Biography: Guri Sohi received a Ph.D in Electrical and Computer Engineering from the University of Illinois, and has been a faculty member at the University of Wisconsin-Madison since 1985. He is currently the John P. Morgridge Professor and the E. David Cronon Professor of Computer Sciences in the Computer Sciences and Electrical and Computer Engineering departments. He served as the Department Chair of the Computer Sciences department from 2004 through 2008.

Sohi's research has been in the design of high-performance computer systems. He has co-authored several papers and patents that have influenced both researchers and commercial microprocessors. In the mid 1980s, while most computer architects were investigating in-order processors, he investigated out-of-order processors. His paper "Instruction Issue Logic for High-Performance, Interruptible Pipelined Processors" (in ISCA 1987) articulated a model for a dynamically-scheduled processor supporting precise exceptions, a model that was widely adopted by several microprocessor manufacturers. (This paper, and the journal version in IEEE Trans. on Computers, March 1990, have been referenced by over 150 U.S. patents. Click here to see the list.) His paper "High Bandwidth Data Memory Systems for Superscalar Processors" (in ASPLOS 1991) argued for non-blocking (or lockup-free) caches, and was instrumental in influencing high-end microprocessors to switch from blocking to non-blocking caches. In the early 1990s while other computer architects started investigating out-of-order processors he proposed the concept of multiscalar processors and thread-level speculation in his papers "The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism" (in ISCA 1992) and "Multiscalar Processors" (in ISCA 1995). Thread-level speculation and its variants are currently one of the most active areas of research in computer architecture. His paper "Dynamic Speculation and Synchronization of Data Dependences" (in ISCA 1997) introduced the idea of memory dependence prediction, an idea that was used in the Alpha processor designs and is being considered by others. His paper "Dynamic Instruction Reuse" (in ISCA 1997) proposed the concept of instruction reuse, another area of active research. He and his students also had the first academic proposal for trace caches. Sohi's research group also developed the Simplescalar simulator, a simulation toolset that is widely used for research and instruction.

Sohi has interacted heavily with industry. Over the years he has discussed his research with architects and given talks in design groups at most of the leading microprocessor manufacturers, including Digital Equipment, HaL, Hewlett-Packard, IBM, Intel, MIPS, Motorola, Silicon Graphics, and Sun Microsystems.

He edited "25 Years of the International Symposium on Computer Architecture - Selected Papers" published by ACM, and recently co-edited (with Mark Hill and Norm Jouppi) "Readings in Computer Architecture" published by Morgan Kaufmann Publishers.

Sohi has graduated 18 Ph.D students, many of whom currently hold academic positions at leading research universities (Illinois, Maryland, Michigan, Pennsylvania, Purdue, and Toronto). They include six winners of NSF CAREER awards and a winner of a Sloan Research Fellowship. He continues to lead a research group investigating different models for speculative multithreading, approximate programs, value communication prediction, chip multiprocessing, and other innovations for future microprocessors.

He received the 1999 ACM SIGARCH Maurice Wilkes award "for seminal contributions in the areas of high issue rate processors and instruction level parallelism". At the University of Wisconsin he was selected as a Vilas Associate in 1997, won the WARF Kellett Mid-Career Faculty Researcher award in 2000 and was selected a WARF Named Professor (E. David Cronon Professor of Computer Sciences) in 2007. He is a Fellow of the ACM and a Fellow of the IEEE and a member of the National Academy of Engineering.

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