--This is code describes a simple state machine which outputs a 1 when
--the sequence 101 has been detected on a serial input

library ieee;
use ieee.std_logic_1164.all;

--Define the "black box" for the object
entity det_101 is port (
  signal clk, s, reset: in std_logic;
  signal q:             out std_logic
);
end det_101;

--Define what's inside the box, in this case it's called version1
architecture version1 of det_101 is

--Define internal signals to be used
  type state_type is (s0, s1, s2, S3);	    --define an enumeration for states
  signal cur_state, next_state: state_type; --Cur_tate is the current state
begin

--state_logic is evaluated when state or s changes
--this is the logic that goes before the ff's and decides the next state
--and the output
  state_logic:process (cur_state, s)

  begin
    case cur_state is
	when s0 =>
	   q <= '0';			--list what happens at each state
	   if s = '1' then
		next_state <= s1;
	   else
		next_state <= s0;
	   end if;

	when s1 =>
	   q <= '0';
	   if s = '1' then
		next_state <= s1;
	   else
		next_state <= s2;
	   end if;

	when s2 =>
	     q <= '0';
	   if s = '1' then
		next_state <= s3;
	   else
		next_state <= s0;
	   end if;

	when s3 =>
	     q <= '1';
	   if s = '1' then
		next_state <= s1;
	   else
		next_state <= s2;
	   end if;

    end case;
  end process state_logic;

--state_register defines "ff's" that are updated when clk or reset changes
  state_register:process (clk, reset)
  begin
     if reset = '1' then		--when reset goes high, goto s0
	cur_state <= s0;
     elsif rising_edge(clk) then	--on a rising edge, store new state
	cur_state <= next_state;
     end if;
  end process state_register;

end version1;