Problem 1

Implement a sequence detector in Verilog using a behavioral description. It should be a Moore model machine, in which the output is dependent only on the state in which the circuit is and not the current input. The sequence detector must detect the last three numbers of your student ID, encoded in binary, and zero extended to 10 bits. For example, if the last three numbers are 949, the circuit should detect 11 1011 0101. If the last three numbers are 003, the circuit should detect 00 0000 0011. The circuit output should be high only after the entire sequence has been detected.

Please make a note of the sequence that your model detects.

module seq_detect(input in, input clk, input reset, output out);

   reg[3:0] state, next_state;

   parameter S0 = 4'h0;
   parameter S1 = 4'h1;
   parameter S2 = 4'h2;
   parameter S3 = 4'h3;
   parameter S4 = 4'h4;
   parameter S5 = 4'h5;
   parameter S6 = 4'h6;
   parameter S7 = 4'h7;
   parameter S8 = 4'h8;
   parameter S9 = 4'h9;
   parameter S10 = 4'hA;

   assign out = state[3] & ~state[2] & state[1] & ~state[0];

   always @(posedge clk)
   begin
     if (reset)  state <= S0;
     else        state <= next_state;
   end

   always @(state, in)
   case(state)
     S0:  if(in)  next_state = S1;
          else    next_state = S0;
     S1:  if(in)  next_state = S2;
          else    next_state = S0;
     S2:  if(in)  next_state = S3;
          else    next_state = S0;
     S3:  if(in)  next_state = S3;
          else    next_state = S4;
     S4:  if(in)  next_state = S5;
          else    next_state = S0;
     S5:  if(in)  next_state = S1;
          else    next_state = S6;
     S6:  if(in)  next_state = S7;
          else    next_state = S0;
     S7:  if(in)  next_state = S8;
          else    next_state = S0;
     S8:  if(in)  next_state = S3;
          else    next_state = S9;
     S9:  if(in)  next_state = S10;
          else    next_state = S0;
     S10: if(in)  next_state = S1;
          else    next_state = S0;

endmodule

Problem 2

Your design should use only 4-to-1 multiplexors, decoders, and some logic gates for the control.

Here's the barrel shifter and its trace:

Here's the schematic for the 2bit shifter...the 1, 4, and 8 bit shifters can be extrapolated from this.

Problem 3

Problem 4.44 on page 330 of H&P

Problem 4

Problem 4.48 on page 330 of H&P

These solutions assume the use of full adders with XOR gates that incur 1 gate delay.

64-bit ripple carry adder:

The first carry is ready at 3T, and each additional carry takes time 2T, so the 63rd carry will be ready in time 3 + 62 * 2T = 127T. The last sum bit will be ready at time 127T + T = 128T

4-bit CLAs connected by ripple carry

Propagates and generates will be ready at time T. The Super P and G from all 4-bit CLAs will be ready at times 2T and 3T, respectively, and the carry-out from the first 4-bit group will be ready at 4T. Each successive ripple carry-out takes an additional 2T, so the 31st rippled carry is ready at time 4T + 14 * 2T = 32T. The 63rd carry will then be ready at time time 34T, and the last sum bit will be ready at time 35T.

16-bit CLAs connected by ripple carry

Propagates and generates will be ready at time T, and the super Ps and Gs from all 16-bit CLAs will be ready at time 3T and 5T, respectively. The carry-out from the first 16-bit group will be ready at time 6T, and each successive ripple carry-out takes an additional 2T. The carry-in to the last 16-bit block will therefore be ready at 6T + 2T * 2 = 10T. The 63rd carry will be ready at time 10T + 2T + 2T = 14T, and the last sum bit will be ready at time 15T.

3-level 64-bit CLA

Propagates and generates will be ready at time T, and the super Ps and Gs from all 16-bit CLAs will be ready at time 3T and 5T, respectively. The 3rd carry-out from the 64-bit carry-lookahead block will be ready at time 7T, the 3rd carry-out from the last 16-bit carry-lookahead block will be ready at time 9T, and the 63rd carry (coming from the last 4-bit carry-lookahead block) will be ready at time 11T. The last sum bit will be ready at time 12T.

Problem 5

This problem is similar to 5.15 from the textbook, except we would like to implement the jump-and-link instruction.

One possible solution: assumes that the return address register is R7

Changes to the datapath: The RegDst mux receives a third input, tied to a constant "7". The control bus for that mux becomes two bits wide. The MemToReg mux receives a third input, tied to the output of the PC register. The control bus for that mux also becomes two bits wide.

The first two clock cycles perform the normal functions. For the third clock cycle, a new branch to the control FSM is added for "jal". This cycle performs the normal functions for Jump completion, but also writes the PC (now containing PC+4) to register R7.

Control signals for the clock cycles:

Problem 6

This problem is similar to 5.15 from the textbook, except we would like to implement the instruction ADD Rs, [Rt], Rd. This is a "register-memory add" instruction, with bits 31-26 specifying the opcode, 25-21 specifying the register Rs, 20-16 specifying the register Rt, and bits 15-11 specifying the register Rd. The instruction performs an add operation with the contents of register Rs as the first operand, the contents at the memory address contained in register Rt (register-indirect addressing at address M[Rt[) as the second operand, and places the result in register Rd.

You must download or photocopy the figures in the textbook. Describe any necessary modifications to the datapath or control signals. Show necessary modifications to the finite state machine from Figure 5.42 on page 396 of the text.

One possible solution:

Changes to the datapath: The ALUSrcB mux is expanded to 5 inputs and the IorD mux is expanded to 3 inputs. The new ALUSrcB input is connected to the output of the memory data register and the new IorD input is connected to the register file's ReadData 2 latch.

The first two clock cycles perform the normal functions. The third clock cycle performs the memory access with the address in Rt. The fourth cycle performs the addition, and the fifth cycle performs the write-back.

Control signals for the clock cycles: