CS/ECE 552: Introduction to Computer Architecture (Spring 2002)
Professor:              Guri Sohi
Teaching Assistant:  Karan Mehra

Final Project:  WISC-SP02 Architecture Implementation
Instruction Set Specification

Description

WISC-SP02 is for the most part a load/store architecture. It is similar to the MIPS R2000 architecture, but is restricted to 16-bit words and a smaller instruction set.  The architecture has 8 registers, R0 through R7.  All instructions and registers are 16 bits wide and the memory is word addressable. The program counter, 16 bits wide,  is separate from the general purpose registers and has a dedicated incrementer.  Reads from register R0 always return 0 and writes to register R0 do not modify R0 . Register R7 is treated as the link register.  When a function call is made--using the JAL or JALR instructions--the return address  (that is, the PC of the next instruction in sequential order) is saved in R7.

Instruction Set Summary

WISC-SP02 supports instructions in three different formats: J-format, I-format, RR-format, RRR-format and RM-format. These are described below.
    J-format    (Jump Format)
    I-format    (Immediate Format)
    RR-format   (Register-Register Format)
    RRR-format  (Register-Register-Register Format)
    RM-format   (Register-Memory Format)
         MM-format   (Memory-Memory Format)

J-format

The J-format is used for jump and branch instructions, using immediate values.
 
J-Format
5 bits 11 bits 
Op Code Displacement

Jump Instructions

The Jump instruction loads the PC with the value found by adding the next PC to the sign-extended displacement.

The Jump-And-Link instruction loads the PC like the Jump instruction. In addition, it saves the return address (that is the address of the sequentially  next instruction) in the link register R7.

The syntax of the jump instructions are:

Branch Instructions

The branch instructions test a general purpose register for zero contents.  If the condition holds, the PC is loaded with the value of the next PC plus the sign-extended displacement. Note that the branch instructions shorten the J-format's displacement to 8 bits in order to make room in the instruction for the source register.

    The syntax of the  branch instructions is:

I-format

I-format instructions use either a destination register, a source register, and a 5-bit immediate value; or a destination register and an 8-bit immediate value.  The two types of I-format instructions are described below.

I-format 1 Instructions

I-format 1
5 bits  3 bits 3 bits 5 bits 
Op Code Rd Rs Immediate

The I-format 1 instructions include Add-Immediate, Subtract-Immediate,  Rotate-Right-Immediate, Shift-Right-Logical-Immediate, Shift-Right-Arithmetic-Immediate,  Load-Immediate, and Store-Immediate.

For Load and Store immediate (LDI & STI) instructions, the effective address of the operand to be read or written is calculated by adding the value in register Rs with the sign-extended immediate value.  The value is loaded to or stored from register Rd.
For the ADDI and SUBI instructions, the immediate is zero extended and the appropriate arithmetic is carried out.
For RORI, SRLI and SRAI, consider only the lower 4 bits of the immediate to carry out the respective function.

The syntax of the I-format 1 instructions is:

I-format 2 Instructions

I-format 2
5 bits  3 bits 8 bits 
Op Code Rd Immediate

The I-format instructions include Load-Upper-Immediate, And-Immediate, Or-Immediate and Xor-Immediate.

The LUI (Load-Upper-Immediate) loads register Rd with the immediate value shifted 8 positions left.  Zeros are shifted into the vacated bit positions.
The ORI instruction loads register Rd with the value of the register Rd OR-ed with the zero-extended immediate value.
ANDI loads register Rd with the value of the register Rd ANDed with the one-extended immediate value.
XORI instruction loads register Rd with the value of the register Rd OR-ed with the sign-extended immediate value.

To load the lower 8 bits of a register, you can use the ORI instruction (assuming that the initial lower 8 bit contents of the register is 0). To obtain the NOT of the value in a register, you can XOR it with an immediate value of all 1's.

The syntax of the I-format 2 instructions are:

RR-format

RR-format instructions use only registers for operands. It consists of two source (Rs  & Rt) and one destination (Rd) register.
 
RR-format
5 bits  3 bits  3 bits  3 bits  2 bits
Op Code Rd Rs Rt  Function code or Unused

ALU and Shift Instructions

The ALU and shift RR-format instructions are similar to I-format 1 instructions, but do not require an immediate value.  In each case, the value of Rt is used in place of the immediate.  No extension of its value is required.  In the case of shift instructions, all but the 4 least-significant bits of Rt are ignored. For AND, OR and XOR, there is only one opcode and the function bits indicate what is the operation. Similarly, for SRL, SRA and ROR, there is only one opcode and the function bits are used to indicate which of the three.

The syntax of the RR-format memory, ALU and shift instructions is:

Jump, Halt, and Return Instructions

The Jump-And-Link-Register instruction saves the return address (the address of the next instruction) in the link register Rd, and loads the PC with the value of register Rs.  The Return instruction is the same as the Jump-Register instruction, but the target register defaults to R7.   The HALT instruction halts the processor.  When the HALT instruction is executed, the state of the machine should be frozen. All enable signals to various blocks should be de-asserted. One way to do this is to AND the system clock with zero.

The syntax of the RR-format branch, return and halt instructions is:

RRR-format

RRR-format instructions use only registers for operands. The Rd register operand is a source and destination register. Rs and Rt are also source registers.

RRR-format

5 bits 3 bits  3 bits 3 bits 2 bits
Op Code Rd Rs Rt Function code or Unused

The RRR-format instructions include the ADDT and SUBT instruction. The ADDT and SUBT instructions treat Rd as a source and destination register. The resulting value is stored in Rd and it is the sum (or difference) of Rd, Rs and Rt.

The syntax of the RRR-format ALU instructions is:

RM-format

RM-format instructions use register and memory operands.

RM-format

5 bits 3 bits 3 bits 3 bits 2 bits
Op Code Rd Rs Rt Function code or Unused

The RM-format instructions include the ADDM and SUBM instruction. The ADDM and SUBM instructions treat the Rt register value as a memory operand. That is the resulting value is stored in Rd and is the sum (or difference) of Rs and the value in memory location Rt.

The syntax of the RM-format ALU instructions is:

MM-format

MM-format instructions use memory operands.

MM-format

5 bits 3 bits 3 bits 3 bits 2 bits
Op Code Rd Rs unused Function code or Unused

The MM-format instructions includes the MMOVE instruction. The MMOVE instruction transfers the memory value at the memory location pointed by register Rs to the memory value at the location pointed by Rd.

The syntax of the RM-format ALU and shift instructions is:

WISC-SP02 Instruction Set Summary

 
Instruction Format Syntax Semantics
00000 xxxxxxxxxxx HALT Freeze the processor state
     
00010 ddd sss iiiii ADDI   Rd, Rs, immediate Rd <- Rs + I(zero ext.)
00011 ddd sss iiiii SUBI   Rd, Rs, immediate Rd <- Rs - I(zero ext.) 
     
00100 ddd iiiiiiii LUI    Rd, immediate Rd <- (I <<(zero filled) 8)
00101 ddd sss iiiii RORI   Rd, Rs, immediate Rd <- Rs >> (rotate) I
00110 ddd sss iiiii SRLI   Rd, Rs, immediate Rd <- Rs >> I
00111 ddd sss iiiii SRAI   Rd, Rs, immediate Rd <- Rs >>(arithmetic) I
01000 ddd iiiiiiii ANDI   Rd, immediate Rd <- Rd AND I(one ext.)
01001 ddd iiiiiiii ORI    Rd, immediate Rd <- Rd OR I(zero ext.)
01010 ddd iiiiiiii XORI   Rd, immediate Rd <- Rd XOR I(sign ext.)
     
01011 ddd sss ttt 00 ADD    Rd, Rs, Rt Rd <- Rs + Rt 
01011 ddd sss ttt 01 ADDT   Rd, Rs,Rt Rd <- Rd + Rs + Rt
01011 ddd sss ttt 10 SUB    Rd, Rs, Rt Rd <- Rs - Rt 
01011 ddd sss ttt 11 SUBT   Rd, Rs, Rt Rd <- Rd - Rs - Rt 
01100 ddd sss ttt 00 ADDM   Rd, Rs, Rt Rd <- Rs + mem[Rt]
01100 ddd sss ttt 10 SUBM   Rd, Rs, Rt Rd <- Rs - mem[Rt]
01110 ddd sss ttt 01 AND    Rd, Rs, Rt Rd <- Rs AND Rt
01110 ddd sss ttt 10 OR     Rd, Rs, Rt Rd <- Rs OR Rt
01110 ddd sss ttt 11 XOR    Rd, Rs, Rt Rd <- Rs XOR Rt
     
01111 ddd sss ttt 01 ROR    Rd, Rs, Rt Rd <- Rs >> (rotate)  Rt
01111 ddd sss ttt 10 SRL    Rd, Rs, Rt Rd <- Rs >> Rt
01111 ddd sss ttt 11 SRA    Rd, Rs, Rt Rd <- Rs >>(arithmetic) Rt
     
10000 sss dddddddd  BEQZ   Rs, displacement if (Rs == 0) then PC <- PC(next) + I(sign ext.)
10001 sss dddddddd BLTZ   Rs, displacement if (Rs <  0) then PC <- PC(next) + I(sign ext.)
10010 sss dddddddd BLEZ   Rs, displacement if (Rs <=  0) then PC <- PC(next) + I(sign ext.)
     
10100 xxxxxxxxxxx RET PC <- R7
10101 ddddddddddd J     displacement PC <- PC(next) + D(sign ext.)
10110 ddddddddddd JAL   displacement R7 <- PC(next) PC <- PC(next) + D(sign ext.)
10111 ddd sss xxxxx JALR  Rd Rs Rd <- PC(next)  PC <- Rs
11000 ddd sss xxxxx JR    Rd PC <- Rd
11001 ddd sss xxxxx  MMOVE Rd,RS Mem[Rd] <- Mem[Rs]
11010 ddd sss iiiii LDI   Rd, Rs, immediate Rd <- Mem[Rs + I(sign ext.)] 
11011 ddd sss iiiii STI   Rd, Rs, immediate Mem[Rs + I(sign ext.)] <- Rd 
11100 ddd sss ttt 00 LD    Rd, Rs, Rt Rd <- Mem[Rs + Rt]
11100 ddd sss ttt 10 ST    Rd, Rs, Rt Mem[Rs + Rt] <- Rd 
 

Implementation

You will design a multicycle, non-pipelined implementation of the WISC-SP02 Architecture.  Figure 5.33 on page 383 of the course text is a good place to start. I suggest you start with the basic control scheme discussed on pages 385-88. It defines a 5 cycle control sequence for the multicycle processor.

You may use the modules you designed in previous homeworks for this project.  If there were errors in your modules, you need to fix them.  An error caused in the results of the final project by an earlier error will be considered to be an error in the project.  Do not rely on my having found all errors in earlier work.  In addition to the correction of errors, you may need to make other modifications.

After you have completed your multicycle, non-pipelined implementation, you may implement a pipelined version of the architecture for extra credit. The pipeline will have five stages:

  1. Instruction fetch (IF)
  2. Instruction decode/register fetch (ID)
  3. Execute/address calculation (EX)
  4. Memory access (MEM)
  5. Write back (WB)
The single-cycle datapath is described in figure 6.10 on page 450 of the second edition of the course text.  The pipelined version of this datapath is described in figure 6.12 on page 452.

Be sure that the non-pipelined version is functional before you try the pipelined design.  While designing the non-pipelined version, make considerations that will allow for an easy conversion to the pipelined version.  There are some useful notes for creating a pipelined version of the datapath in

~cs552-2/public/html/Project/Notes.html

Please also refer to the Grading Specification sheet.

Assembler and Test Programs

  See web page