Gurindar S. Sohi

Below are recent papers co-authored by Gurindar S. Sohi.

Go to Year:

• 2002, 2001, 2000.
• 1999, 1998, 1997, 1996, 1995.
• 1994, 1993, 1992.

2002

• Characterizing and Predicting Value Degree of Use
  J. Adam Butts and G.S. Sohi
  35th International Symposium on Microarchitecture (MICRO-35), Nov. 2002.
  

• A Quantitative Framework for Automated Pre-Execution Thread Selection
  Amir Roth and G.S. Sohi
  35th International Symposium on Microarchitecture (MICRO-35), Nov. 2002.
  

• Master/Slave Speculative Parallelization
  Craig Zilles and G.S. Sohi
  35th International Symposium on Microarchitecture (MICRO-35), Nov. 2002.
  

• Dynamic Dead-Instruction Detection and Elimination
  J. Adam Butts and G.S. Sohi
  10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), Oct 2002.
  

• Out-of-Order Fetch Using Multiple Sequencers
  Paramjit Oberoi and G. S. Sohi
  International Conference on Parallel Processing (ICPP), August 2002.

2001

• Speculative Versioning Cache
  T. N. Vijaykumar, S. Gopal, J. E. Smith and G. S. Sohi
  IEEE Transactions on Parallel and Distributed Systems, vol. 12, no. 12, December 2001.

• Micro-Architectural Innovations: Boosting Processor Performance Beyond Technology Scaling
  Andreas Moshovos and G. S. Sohi
  Proceedings of the IEEE, vol. 89, no. 11, November 2001.

• Execution-based Prediction Using Speculative Slices
  Craig B. Zilles and Gurindar S. Sohi
  28th International Symposium on Computer Architecture (ISCA-28), 2000.
  Abstract

• Speculative Multithreaded Processors
  G. S. Sohi and Amir Roth
  IEEE Computer, vol. 34, no. 4, April 2001.

• Speculative Data-Driven Multithreading
  Amir Roth and G. S. Sohi
  Seventh International Symposium on High-Performance Computer Architecture (HPCA-7), Jan. 2001.
  

• A Programmable Co-processor for Profiling
  Craig Zilles and G. S. Sohi
  Seventh International Symposium on High-Performance Computer Architecture (HPCA-7), Jan. 2001.
  

2000

• Speculative Multithreaded Processors (PDF)
  G. S. Sohi and Amir Roth
  Int. Conf. on High Performance Computing (HiPC), December 2000
  

• A Static Power Model for Architects (PDF)
  J. Adam Butts and G.S. Sohi
  33rd International Symposium on Microarchitecture (MICRO-33), Dec. 2000.
  

• Register Integration: A Simple and Efficient Implementation of Squash Reuse (PDF)
  Amir Roth and G. S. Sohi
  33rd International Symposium on Microarchitecture (MICRO-33), Dec. 2000.
  

• Speculative Miss/Execute Decoupling (PDF)
  Amir Roth, Craig B. Zilles and G. S. Sohi
  MEDEA Workshop, October 2000
  

• Microprocessors--10 years back, 10 years ahead
  G. S. Sohi
  Conference at the Occasion of Dagstuhl's 10th Anniversary. Conference proceedings were published as LNCS volume 2000 by Springer-Verlang.
  

• Understanding the Backward Slices of Performance Degrading Instructions
  Craig B. Zilles and Gurindar S. Sohi
  27th International Symposium on Computer Architecture (ISCA-27), 2000.
  Abstract

• Memory Dependence Prediction in Multimedia Applications
  Andreas Moshovos and Gurindar S. Sohi
  International Journal of Parallel Programming, May 2000.
  

• Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors
  Andreas Moshovos and Gurindar S. Sohi
  Sixth International Symposium on High-Performance Computer Architecture (HPCA-6), Jan. 2000.
  

1999

• Read-After-Read Memory Dependence Prediction (PDF)
  Andreas Moshovos and Gurindar S. Sohi
  32nd International Symposium on Microarchitecture (MICRO-32), Nov 1999.
  

• The Use of Multithreading for Exception Handling
  Craig B. Zilles, Joel S. Emer, and Gurindar S. Sohi
  32nd International Symposium on Microarchitecture (MICRO-32), Nov 1999.
  Abstract

• Speculative Memory Cloaking and Bypassing (PDF)
  Andreas Moshovos and Gurindar S. Sohi
  International Journal of Parallel Programming, October 1999.
  

• Task Selection for the Multiscalar Architecture
  T. N. Vijaykumar and G. S. Sohi, Journal of Parallel and Distributed Computing (JPDC), pages 132-158, vol. 58, No.2, August 1999, pp. 132-158.
  

• Improving Virtual Function Call Target Prediction via Dependence-Based Pre-Computation
  Amir Roth, Andreas Moshovos and Gurindar S. Sohi
  International Conference on Supercomputing (ICS), June 20-25, 1999.
  Abstract

• Effective Jump-Pointer Prefetching for Linked Data Structures
  Amir Roth and Gurindar S. Sohi
  26th International Symposium on Computer Architecture (ISCA-25), May 2-4 1999.
  Abstract

1998

• Understanding the Differences Between Value Prediction and Instruction Reuse
  Avinash Sodani and Gurindar S. Sohi
  31th International Symposium on Microarchitecture (MICRO-31), Nov-Dec 1998.
  Abstract.

• Task Selection for a Multiscalar Processor
  T.N. Vijaykumar and Gurindar S. Sohi
  31th International Symposium on Microarchitecture (MICRO-31), Nov-Dec 1998.
  Abstract.

• Dependence Based Prefetching for Linked Data Structures
  Amir Roth, Andreas Moshovos, and Gurindar S. Sohi
  8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct 1998.
  Abstract.

• An Empirical Analysis of Instruction Repetition
  Avinash Sodani and Gurindar S. Sohi
  8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct 1998.
  Abstract.

• Speculative Versioning Cache
  Sridhar Gopal, T.N. Vijaykumar, J. E. Smith and G. S. Sohi
  Fourth International Symposium on High-Performance Computer Architecture (HPCA-4), Feb 1998.
  Abstract Technical report

1997

• Streamlining Inter-operation Memory Communication via Data Dependence Prediction
  Andreas Moshovos and Gurindar S. Sohi
  30th Annual international Symposium on Microarchitecture (MICRO-30), Dec 1997.
  Abstract

  Dynamic Speculation and Synchronization of Data Dependences ,
  Andreas I. Moshovos, Scott E. Breach, T.N. Vijaykumar, Gurindar S. Sohi, 24th International Symposium on Computer Architecture(ISCA), June 1997. Abstract.

  Dynamic Instruction Reuse ,
  Avinash Sodani and Gurindar S. Sohi, 24th International Symposium on Computer Architecture(ISCA), June 1997. Abstract.

  Computing with Billion Transistor Chips ,
  Gurindar S. Sohi, unpublished note, February 1997.

1996

High-Bandwidth Address Translation for Multiple-Issue Processors,
T. M. Austin and G. S. Sohi, 23rd Annual International Symposium on Computer Architecture, May 1996. An appendix of detailed results is also available.)


A Hardware Mechanism for Dynamic Reordering of Memory References
M. Franklin and G. S. Sohi, IEEE Transactions on Computers, May 1996.

1995

The Microarchitecture of Superscalar Processors
J. E. Smith and G. S. Sohi, in Proceedings of the IEEE, December 1995.

Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency
T. M. Austin and G. S. Sohi, 28th Annual International Symposium on Microarchitecture (MICRO-28), 1995.

Multiscalar Processors,
G. S. Sohi, S. Breach, and T. N. Vijaykumar, 22th International Symposium on Computer Architecture, 1995.

Streamlining Data Cache Access with Fast Address Calculation,
T. M. Austin, D. N. Pnevmatikatos, and G. S. Sohi, 22th International Symposium on Computer Architecture, 1995.

1994

The Anatomy of the Register File in a Multiscalar Processor,
S. Breach, T. N. Vijaykumar, and G. S. Sohi, 27th Annual International Symposium on Microarchitecture (MICRO-27), 1994.

Request Combining in Multiprocessors with Arbitrary Interconnection Networks,
A. Lebeck and G. S. Sohi, in IEEE Transactions on Parallel and Distributed Systems, 1994.

Efficient Detection of All Pointer and Array Access Errors,
T. M. Austin, S. E. Breach and G. S. Sohi, SIGPLAN '94 Conference on Programming Language Design and Implementation, 1994.

Guarded Execution and Branch Prediction in Dynamic ILP Processors,
D. Pnevmatikatos and G. S. Sohi, 21th International Symposium on Computer Architecture, 1994.

1993

Memory Systems,
J. R. Goodman and G. S. Sohi, The Handbook of Electrical Engineering, CRC Press, 1993.

Control Flow Prediction for Dynamic ILP Processors,
D. Pnevmatikatos, M. Franklin and G. S. Sohi, 26th Annual International Symposium on Microarchitecture (MICRO-26), 1993.

Efficient Detection of All Pointer and Array Access Errors
T.M. Austin, S. E. Breach and G. S. Sohi, Technical Report #1197, Computer Sciences Department, University of Wisconsin-Madison, December 1993.

Guarded Execution and Branch Prediction in Dynamic ILP Processors
D. N. Pnevmatikatos and G. S. Sohi, Technical Report #1193, Computer Sciences Department, University of Wisconsin-Madison, November 1993.

Knapsack: A Zero-Cycle Memory Hierarchy Component
T. M. Austin, T. N. Vijaykumar, and G. S. Sohi, Technical Report #1189, Computer Sciences Department, University of Wisconsin-Madison, November 1993.

Tetra: Evaluation of Serial Program Performance on Fine-Grain Parallel Processors
T. M. Austin and G. S. Sohi, Technical Report #1162, Computer Sciences Department, University of Wisconsin-Madison, July 1993.

1992

Register Traffic Analysis for Streamlining Inter-operation Communication in Fine-Grain Parallel Processors,
M. Franklin and G. S. Sohi, 25th Annual International Symposium on Microarchitecture (MICRO-25), 1992.

The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism,
M. Franklin and G. S. Sohi, 19th International Symposium on Computer Architecture, 1992.

Dynamic Dependency Analysis of Ordinary Programs,
T.M. Austin and G. S. Sohi, 19th International Symposium on Computer Architecture, 1992.