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types.hh File Reference
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "debug/Decoder.hh"

Go to the source code of this file.

Classes

struct  std::hash< ArmISA::ExtMachInst >
 

Namespaces

 ArmISA
 
 std
 Overload hash function for BasicBlockRange type.
 

Typedefs

typedef uint32_t ArmISA::MachInst
 
typedef int ArmISA::RegContextParam
 
typedef int ArmISA::RegContextVal
 

Enumerations

enum  ArmISA::ArmShiftType { ArmISA::LSL = 0, ArmISA::LSR, ArmISA::ASR, ArmISA::ROR }
 
enum  ArmISA::ArmExtendType {
  ArmISA::UXTB = 0, ArmISA::UXTH = 1, ArmISA::UXTW = 2, ArmISA::UXTX = 3,
  ArmISA::SXTB = 4, ArmISA::SXTH = 5, ArmISA::SXTW = 6, ArmISA::SXTX = 7
}
 
enum  ArmISA::ConvertType {
  ArmISA::SINGLE_TO_DOUBLE, ArmISA::SINGLE_TO_WORD, ArmISA::SINGLE_TO_LONG, ArmISA::DOUBLE_TO_SINGLE,
  ArmISA::DOUBLE_TO_WORD, ArmISA::DOUBLE_TO_LONG, ArmISA::LONG_TO_SINGLE, ArmISA::LONG_TO_DOUBLE,
  ArmISA::LONG_TO_WORD, ArmISA::LONG_TO_PS, ArmISA::WORD_TO_SINGLE, ArmISA::WORD_TO_DOUBLE,
  ArmISA::WORD_TO_LONG, ArmISA::WORD_TO_PS, ArmISA::PL_TO_SINGLE, ArmISA::PU_TO_SINGLE
}
 
enum  ArmISA::RoundMode { ArmISA::RND_ZERO, ArmISA::RND_DOWN, ArmISA::RND_UP, ArmISA::RND_NEAREST }
 
enum  ArmISA::ExceptionLevel { ArmISA::EL0 = 0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3 }
 
enum  ArmISA::OperatingMode {
  ArmISA::MODE_EL0T = 0x0, ArmISA::MODE_EL1T = 0x4, ArmISA::MODE_EL1H = 0x5, ArmISA::MODE_EL2T = 0x8,
  ArmISA::MODE_EL2H = 0x9, ArmISA::MODE_EL3T = 0xC, ArmISA::MODE_EL3H = 0xD, ArmISA::MODE_USER = 16,
  ArmISA::MODE_FIQ = 17, ArmISA::MODE_IRQ = 18, ArmISA::MODE_SVC = 19, ArmISA::MODE_MON = 22,
  ArmISA::MODE_ABORT = 23, ArmISA::MODE_HYP = 26, ArmISA::MODE_UNDEFINED = 27, ArmISA::MODE_SYSTEM = 31,
  ArmISA::MODE_MAXMODE = MODE_SYSTEM
}
 
enum  ArmISA::ExceptionClass {
  ArmISA::EC_INVALID = -1, ArmISA::EC_UNKNOWN = 0x0, ArmISA::EC_TRAPPED_WFI_WFE = 0x1, ArmISA::EC_TRAPPED_CP15_MCR_MRC = 0x3,
  ArmISA::EC_TRAPPED_CP15_MCRR_MRRC = 0x4, ArmISA::EC_TRAPPED_CP14_MCR_MRC = 0x5, ArmISA::EC_TRAPPED_CP14_LDC_STC = 0x6, ArmISA::EC_TRAPPED_HCPTR = 0x7,
  ArmISA::EC_TRAPPED_SIMD_FP = 0x7, ArmISA::EC_TRAPPED_CP10_MRC_VMRS = 0x8, ArmISA::EC_TRAPPED_BXJ = 0xA, ArmISA::EC_TRAPPED_CP14_MCRR_MRRC = 0xC,
  ArmISA::EC_ILLEGAL_INST = 0xE, ArmISA::EC_SVC_TO_HYP = 0x11, ArmISA::EC_SVC = 0x11, ArmISA::EC_HVC = 0x12,
  ArmISA::EC_SMC_TO_HYP = 0x13, ArmISA::EC_SMC = 0x13, ArmISA::EC_SVC_64 = 0x15, ArmISA::EC_HVC_64 = 0x16,
  ArmISA::EC_SMC_64 = 0x17, ArmISA::EC_TRAPPED_MSR_MRS_64 = 0x18, ArmISA::EC_PREFETCH_ABORT_TO_HYP = 0x20, ArmISA::EC_PREFETCH_ABORT_LOWER_EL = 0x20,
  ArmISA::EC_PREFETCH_ABORT_FROM_HYP = 0x21, ArmISA::EC_PREFETCH_ABORT_CURR_EL = 0x21, ArmISA::EC_PC_ALIGNMENT = 0x22, ArmISA::EC_DATA_ABORT_TO_HYP = 0x24,
  ArmISA::EC_DATA_ABORT_LOWER_EL = 0x24, ArmISA::EC_DATA_ABORT_FROM_HYP = 0x25, ArmISA::EC_DATA_ABORT_CURR_EL = 0x25, ArmISA::EC_STACK_PTR_ALIGNMENT = 0x26,
  ArmISA::EC_FP_EXCEPTION = 0x28, ArmISA::EC_FP_EXCEPTION_64 = 0x2C, ArmISA::EC_SERROR = 0x2F
}
 
enum  ArmISA::DecoderFault : std::uint8_t { ArmISA::OK = 0x0, ArmISA::UNALIGNED = 0x1, ArmISA::PANIC = 0x3 }
 Instruction decoder fault codes in ExtMachInst. More...
 

Functions

 ArmISA::BitUnion8 (ITSTATE) Bitfield<7
 
 ArmISA::EndBitUnion (ITSTATE) BitUnion64(ExtMachInst) Bitfield< 63
 
 ArmISA::SubBitUnion (puswl, 24, 20) Bitfield< 24 > prepost
 
 ArmISA::EndSubBitUnion (puswl) Bitfield< 24
 
 ArmISA::EndBitUnion (ExtMachInst) class PCState
 
 ArmISA::BitUnion8 (OperatingMode64) Bitfield< 0 > spX
 
 ArmISA::EndBitUnion (OperatingMode64) static bool inline opModeIs64(OperatingMode mode)
 
static bool ArmISA::opModeIsH (OperatingMode mode)
 
static bool ArmISA::opModeIsT (OperatingMode mode)
 
static ExceptionLevel ArmISA::opModeToEL (OperatingMode mode)
 
static bool ArmISA::badMode (OperatingMode mode)
 
static bool ArmISA::badMode32 (OperatingMode mode)
 

Variables

 ArmISA::cond
 
Bitfield< 3, 0 > ArmISA::mask
 
Bitfield< 7, 2 > ArmISA::top6
 
Bitfield< 1, 0 > ArmISA::bottom2
 
 ArmISA::decoderFault
 
Bitfield< 55, 48 > ArmISA::itstate
 
Bitfield< 55, 52 > ArmISA::itstateCond
 
Bitfield< 51, 48 > ArmISA::itstateMask
 
Bitfield< 41, 40 > ArmISA::fpscrStride
 
Bitfield< 39, 37 > ArmISA::fpscrLen
 
Bitfield< 36 > ArmISA::thumb
 
Bitfield< 35 > ArmISA::bigThumb
 
Bitfield< 34 > ArmISA::aarch64
 
Bitfield< 33 > ArmISA::sevenAndFour
 
Bitfield< 32 > ArmISA::isMisc
 
uint32_t ArmISA::instBits
 
Bitfield< 27, 25 > ArmISA::encoding
 
Bitfield< 25 > ArmISA::useImm
 
Bitfield< 24, 21 > ArmISA::opcode
 
Bitfield< 24, 20 > ArmISA::mediaOpcode
 
Bitfield< 24 > ArmISA::opcode24
 
Bitfield< 24, 23 > ArmISA::opcode24_23
 
Bitfield< 23, 20 > ArmISA::opcode23_20
 
Bitfield< 23, 21 > ArmISA::opcode23_21
 
Bitfield< 20 > ArmISA::opcode20
 
Bitfield< 22 > ArmISA::opcode22
 
Bitfield< 19, 16 > ArmISA::opcode19_16
 
Bitfield< 19 > ArmISA::opcode19
 
Bitfield< 18 > ArmISA::opcode18
 
Bitfield< 15, 12 > ArmISA::opcode15_12
 
Bitfield< 15 > ArmISA::opcode15
 
Bitfield< 7, 4 > ArmISA::miscOpcode
 
Bitfield< 7, 5 > ArmISA::opc2
 
Bitfield< 7 > ArmISA::opcode7
 
Bitfield< 6 > ArmISA::opcode6
 
Bitfield< 4 > ArmISA::opcode4
 
Bitfield< 31, 28 > ArmISA::condCode
 
Bitfield< 20 > ArmISA::sField
 
Bitfield< 19, 16 > ArmISA::rn
 
Bitfield< 15, 12 > ArmISA::rd
 
Bitfield< 15, 12 > ArmISA::rt
 
Bitfield< 11, 7 > ArmISA::shiftSize
 
Bitfield< 6, 5 > ArmISA::shift
 
Bitfield< 3, 0 > ArmISA::rm
 
Bitfield< 23 > ArmISA::up
 
Bitfield< 22 > ArmISA::psruser
 
Bitfield< 21 > ArmISA::writeback
 
Bitfield< 20 > ArmISA::loadOp
 
 ArmISA::pubwl
 
Bitfield< 7, 0 > ArmISA::imm
 
Bitfield< 11, 8 > ArmISA::rotate
 
Bitfield< 11, 0 > ArmISA::immed11_0
 
Bitfield< 7, 0 > ArmISA::immed7_0
 
Bitfield< 11, 8 > ArmISA::immedHi11_8
 
Bitfield< 3, 0 > ArmISA::immedLo3_0
 
Bitfield< 15, 0 > ArmISA::regList
 
Bitfield< 23, 0 > ArmISA::offset
 
Bitfield< 23, 0 > ArmISA::immed23_0
 
Bitfield< 11, 8 > ArmISA::cpNum
 
Bitfield< 18, 16 > ArmISA::fn
 
Bitfield< 14, 12 > ArmISA::fd
 
Bitfield< 3 > ArmISA::fpRegImm
 
Bitfield< 3, 0 > ArmISA::fm
 
Bitfield< 2, 0 > ArmISA::fpImm
 
Bitfield< 24, 20 > ArmISA::punwl
 
Bitfield< 15, 8 > ArmISA::m5Func
 
Bitfield< 15, 13 > ArmISA::topcode15_13
 
Bitfield< 13, 11 > ArmISA::topcode13_11
 
Bitfield< 12, 11 > ArmISA::topcode12_11
 
Bitfield< 12, 10 > ArmISA::topcode12_10
 
Bitfield< 11, 9 > ArmISA::topcode11_9
 
Bitfield< 11, 8 > ArmISA::topcode11_8
 
Bitfield< 10, 9 > ArmISA::topcode10_9
 
Bitfield< 10, 8 > ArmISA::topcode10_8
 
Bitfield< 9, 6 > ArmISA::topcode9_6
 
Bitfield< 7 > ArmISA::topcode7
 
Bitfield< 7, 6 > ArmISA::topcode7_6
 
Bitfield< 7, 5 > ArmISA::topcode7_5
 
Bitfield< 7, 4 > ArmISA::topcode7_4
 
Bitfield< 3, 0 > ArmISA::topcode3_0
 
Bitfield< 28, 27 > ArmISA::htopcode12_11
 
Bitfield< 26, 25 > ArmISA::htopcode10_9
 
Bitfield< 25 > ArmISA::htopcode9
 
Bitfield< 25, 24 > ArmISA::htopcode9_8
 
Bitfield< 25, 21 > ArmISA::htopcode9_5
 
Bitfield< 25, 20 > ArmISA::htopcode9_4
 
Bitfield< 24 > ArmISA::htopcode8
 
Bitfield< 24, 23 > ArmISA::htopcode8_7
 
Bitfield< 24, 22 > ArmISA::htopcode8_6
 
Bitfield< 24, 21 > ArmISA::htopcode8_5
 
Bitfield< 23 > ArmISA::htopcode7
 
Bitfield< 23, 21 > ArmISA::htopcode7_5
 
Bitfield< 22 > ArmISA::htopcode6
 
Bitfield< 22, 21 > ArmISA::htopcode6_5
 
Bitfield< 21, 20 > ArmISA::htopcode5_4
 
Bitfield< 20 > ArmISA::htopcode4
 
Bitfield< 19, 16 > ArmISA::htrn
 
Bitfield< 20 > ArmISA::hts
 
Bitfield< 15 > ArmISA::ltopcode15
 
Bitfield< 11, 8 > ArmISA::ltopcode11_8
 
Bitfield< 7, 6 > ArmISA::ltopcode7_6
 
Bitfield< 7, 4 > ArmISA::ltopcode7_4
 
Bitfield< 4 > ArmISA::ltopcode4
 
Bitfield< 11, 8 > ArmISA::ltrd
 
Bitfield< 11, 8 > ArmISA::ltcoproc
 

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