DRAMSim2 Member List

This is the complete list of members for DRAMSim2, including all inherited members.

_currPwrState	ClockedObject	protected
_params	SimObject	protected
_system	AbstractMemory	protected
AbstractMemory(const Params *p)	AbstractMemory
access(PacketPtr pkt)	AbstractMemory
accessAndRespond(PacketPtr pkt)	DRAMSim2	private
addLockedAddr(LockedAddr addr)	AbstractMemory	inline
bwInstRead	AbstractMemory	protected
bwRead	AbstractMemory	protected
bwTotal	AbstractMemory	protected
bwWrite	AbstractMemory	protected
bytesInstRead	AbstractMemory	protected
bytesRead	AbstractMemory	protected
bytesWritten	AbstractMemory	protected
checkLockedAddrList(PacketPtr pkt)	AbstractMemory	protected
ckptCount	Serializable	static
ckptMaxCount	Serializable	static
ckptPrevCount	Serializable	static
Clocked(ClockDomain &clk_domain)	Clocked	inlineprotected
Clocked(Clocked &)=delete	Clocked	protected
clockEdge(Cycles cycles=Cycles(0)) const	Clocked	inline
ClockedObject(const ClockedObjectParams *p)	ClockedObject
clockPeriod() const	Clocked	inline
computeStats()	ClockedObject
confTableReported	AbstractMemory	protected
curCycle() const	Clocked	inline
currentSection()	Serializable	static
cyclesToTicks(Cycles c) const	Clocked	inline
deschedule(Event &event)	EventManager	inline
deschedule(Event *event)	EventManager	inline
drain() override	DRAMSim2	virtual
Drainable()	Drainable	protected
drainResume()	Drainable	inlineprotectedvirtual
drainState() const	Drainable	inline
DRAMSim2(const Params *p)	DRAMSim2
EventManager(EventManager &em)	EventManager	inline
EventManager(EventManager *em)	EventManager	inline
EventManager(EventQueue *eq)	EventManager	inline
eventq	EventManager	protected
eventQueue() const	EventManager	inline
find(const char *name)	SimObject	static
frequency() const	Clocked	inline
functionalAccess(PacketPtr pkt)	AbstractMemory
getAddrRange() const	AbstractMemory
getLockedAddrList() const	AbstractMemory	inline
getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)	MemObject	virtual
getProbeManager()	SimObject
getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) override	DRAMSim2	virtual
inAddrMap	AbstractMemory	protected
init() override	DRAMSim2	virtual
initState()	SimObject	virtual
isConfReported() const	AbstractMemory	inline
isInAddrMap() const	AbstractMemory	inline
isKvmMap() const	AbstractMemory	inline
isNull() const	AbstractMemory	inline
kvmMap	AbstractMemory	protected
loadState(CheckpointIn &cp)	SimObject	virtual
lockedAddrList	AbstractMemory	protected
memInvalidate()	SimObject	inlinevirtual
MemObject(const Params *params)	MemObject
memWriteback()	SimObject	inlinevirtual
name() const	SimObject	inlinevirtual
nbrOutstanding() const	DRAMSim2	private
nbrOutstandingReads	DRAMSim2	private
nbrOutstandingWrites	DRAMSim2	private
nextCycle() const	Clocked	inline
notifyFork()	Drainable	inlinevirtual
numOther	AbstractMemory	protected
numPwrStateTransitions	ClockedObject	protected
numReads	AbstractMemory	protected
numWrites	AbstractMemory	protected
MemObject::operator=(Clocked &)=delete	Clocked	protected
outstandingReads	DRAMSim2	private
outstandingWrites	DRAMSim2	private
Params typedef	DRAMSim2
params() const	AbstractMemory	inline
pendingDelete	DRAMSim2	private
pmemAddr	AbstractMemory	protected
port	DRAMSim2	private
prvEvalTick	ClockedObject	protected
pwrState() const	ClockedObject	inline
pwrState(Enums::PwrState)	ClockedObject
pwrStateClkGateDist	ClockedObject	protected
pwrStateName() const	ClockedObject	inline
pwrStateResidencyTicks	ClockedObject	protected
pwrStateWeights() const	ClockedObject
range	AbstractMemory	protected
readComplete(unsigned id, uint64_t addr, uint64_t cycle)	DRAMSim2
recvAtomic(PacketPtr pkt)	DRAMSim2	protected
recvFunctional(PacketPtr pkt)	DRAMSim2	protected
recvRespRetry()	DRAMSim2	protected
recvTimingReq(PacketPtr pkt)	DRAMSim2	protected
regProbeListeners()	SimObject	virtual
regProbePoints()	SimObject	virtual
regStats() override	AbstractMemory	virtual
reschedule(Event &event, Tick when, bool always=false)	EventManager	inline
reschedule(Event *event, Tick when, bool always=false)	EventManager	inline
resetClock() const	Clocked	inlineprotected
resetStats()	SimObject	virtual
responseQueue	DRAMSim2	private
retryReq	DRAMSim2	private
retryResp	DRAMSim2	private
schedule(Event &event, Tick when)	EventManager	inline
schedule(Event *event, Tick when)	EventManager	inline
sendResponse()	DRAMSim2	private
sendResponseEvent	DRAMSim2	private
Serializable()	Serializable
serialize(CheckpointOut &cp) const override	ClockedObject	virtual
serializeAll(CheckpointOut &cp)	SimObject	static
Serializable::serializeAll(const std::string &cpt_dir)	Serializable	static
serializeSection(CheckpointOut &cp, const char *name) const	Serializable
serializeSection(CheckpointOut &cp, const std::string &name) const	Serializable	inline
setBackingStore(uint8_t *pmem_addr)	AbstractMemory
setCurTick(Tick newVal)	EventManager	inline
signalDrainDone() const	Drainable	inlineprotected
SimObject(const Params *_params)	SimObject
size() const	AbstractMemory	inline
start() const	AbstractMemory	inline
startTick	DRAMSim2	private
startup() override	DRAMSim2	virtual
system() const	AbstractMemory	inline
system(System *sys)	AbstractMemory	inline
tick()	DRAMSim2	private
tickEvent	DRAMSim2	private
ticksToCycles(Tick t) const	Clocked	inline
trackLoadLocked(PacketPtr pkt)	AbstractMemory	protected
unserialize(CheckpointIn &cp) override	ClockedObject	virtual
unserializeGlobals(CheckpointIn &cp)	Serializable	static
unserializeSection(CheckpointIn &cp, const char *name)	Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)	Serializable	inline
updateClockPeriod() const	Clocked	inline
voltage() const	Clocked	inline
wakeupEventQueue(Tick when=(Tick)-1)	EventManager	inline
wrapper	DRAMSim2	private
writeComplete(unsigned id, uint64_t addr, uint64_t cycle)	DRAMSim2
writeOK(PacketPtr pkt)	AbstractMemory	inlineprotected
~AbstractMemory()	AbstractMemory	inlinevirtual
~Clocked()	Clocked	inlineprotectedvirtual
~Drainable()	Drainable	protectedvirtual
~Serializable()	Serializable	virtual
~SimObject()	SimObject	virtual