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SimpleMemory Member List

This is the complete list of members for SimpleMemory, including all inherited members.

_currPwrStateClockedObjectprotected
_paramsSimObjectprotected
_systemAbstractMemoryprotected
AbstractMemory(const Params *p)AbstractMemory
access(PacketPtr pkt)AbstractMemory
addLockedAddr(LockedAddr addr)AbstractMemoryinline
bandwidthSimpleMemoryprivate
bwInstReadAbstractMemoryprotected
bwReadAbstractMemoryprotected
bwTotalAbstractMemoryprotected
bwWriteAbstractMemoryprotected
bytesInstReadAbstractMemoryprotected
bytesReadAbstractMemoryprotected
bytesWrittenAbstractMemoryprotected
checkLockedAddrList(PacketPtr pkt)AbstractMemoryprotected
ckptCountSerializablestatic
ckptMaxCountSerializablestatic
ckptPrevCountSerializablestatic
Clocked(ClockDomain &clk_domain)Clockedinlineprotected
Clocked(Clocked &)=deleteClockedprotected
clockEdge(Cycles cycles=Cycles(0)) const Clockedinline
ClockedObject(const ClockedObjectParams *p)ClockedObject
clockPeriod() const Clockedinline
computeStats()ClockedObject
confTableReportedAbstractMemoryprotected
curCycle() const Clockedinline
currentSection()Serializablestatic
cyclesToTicks(Cycles c) const Clockedinline
dequeue()SimpleMemoryprivate
dequeueEventSimpleMemoryprivate
deschedule(Event &event)EventManagerinline
deschedule(Event *event)EventManagerinline
drain() overrideSimpleMemoryvirtual
Drainable()Drainableprotected
drainResume()Drainableinlineprotectedvirtual
drainState() const Drainableinline
EventManager(EventManager &em)EventManagerinline
EventManager(EventManager *em)EventManagerinline
EventManager(EventQueue *eq)EventManagerinline
eventqEventManagerprotected
eventQueue() const EventManagerinline
find(const char *name)SimObjectstatic
frequency() const Clockedinline
functionalAccess(PacketPtr pkt)AbstractMemory
getAddrRange() const AbstractMemory
getLatency() const SimpleMemoryprivate
getLockedAddrList() const AbstractMemoryinline
getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)MemObjectvirtual
getProbeManager()SimObject
getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) overrideSimpleMemoryvirtual
inAddrMapAbstractMemoryprotected
init() overrideSimpleMemoryvirtual
initState()SimObjectvirtual
isBusySimpleMemoryprivate
isConfReported() const AbstractMemoryinline
isInAddrMap() const AbstractMemoryinline
isKvmMap() const AbstractMemoryinline
isNull() const AbstractMemoryinline
kvmMapAbstractMemoryprotected
latencySimpleMemoryprivate
latency_varSimpleMemoryprivate
loadState(CheckpointIn &cp)SimObjectvirtual
lockedAddrListAbstractMemoryprotected
memInvalidate()SimObjectinlinevirtual
MemObject(const Params *params)MemObject
memWriteback()SimObjectinlinevirtual
name() const SimObjectinlinevirtual
nextCycle() const Clockedinline
notifyFork()Drainableinlinevirtual
numOtherAbstractMemoryprotected
numPwrStateTransitionsClockedObjectprotected
numReadsAbstractMemoryprotected
numWritesAbstractMemoryprotected
MemObject::operator=(Clocked &)=deleteClockedprotected
packetQueueSimpleMemoryprivate
Params typedefAbstractMemory
params() const AbstractMemoryinline
pendingDeleteSimpleMemoryprivate
pmemAddrAbstractMemoryprotected
portSimpleMemoryprivate
prvEvalTickClockedObjectprotected
pwrState() const ClockedObjectinline
pwrState(Enums::PwrState)ClockedObject
pwrStateClkGateDistClockedObjectprotected
pwrStateName() const ClockedObjectinline
pwrStateResidencyTicksClockedObjectprotected
pwrStateWeights() const ClockedObject
rangeAbstractMemoryprotected
recvAtomic(PacketPtr pkt)SimpleMemoryprotected
recvFunctional(PacketPtr pkt)SimpleMemoryprotected
recvRespRetry()SimpleMemoryprotected
recvTimingReq(PacketPtr pkt)SimpleMemoryprotected
regProbeListeners()SimObjectvirtual
regProbePoints()SimObjectvirtual
regStats() overrideAbstractMemoryvirtual
release()SimpleMemoryprivate
releaseEventSimpleMemoryprivate
reschedule(Event &event, Tick when, bool always=false)EventManagerinline
reschedule(Event *event, Tick when, bool always=false)EventManagerinline
resetClock() const Clockedinlineprotected
resetStats()SimObjectvirtual
retryReqSimpleMemoryprivate
retryRespSimpleMemoryprivate
schedule(Event &event, Tick when)EventManagerinline
schedule(Event *event, Tick when)EventManagerinline
Serializable()Serializable
serialize(CheckpointOut &cp) const overrideClockedObjectvirtual
serializeAll(CheckpointOut &cp)SimObjectstatic
Serializable::serializeAll(const std::string &cpt_dir)Serializablestatic
serializeSection(CheckpointOut &cp, const char *name) const Serializable
serializeSection(CheckpointOut &cp, const std::string &name) const Serializableinline
setBackingStore(uint8_t *pmem_addr)AbstractMemory
setCurTick(Tick newVal)EventManagerinline
signalDrainDone() const Drainableinlineprotected
SimObject(const Params *_params)SimObject
SimpleMemory(const SimpleMemoryParams *p)SimpleMemory
size() const AbstractMemoryinline
start() const AbstractMemoryinline
startup()SimObjectvirtual
system() const AbstractMemoryinline
system(System *sys)AbstractMemoryinline
ticksToCycles(Tick t) const Clockedinline
trackLoadLocked(PacketPtr pkt)AbstractMemoryprotected
unserialize(CheckpointIn &cp) overrideClockedObjectvirtual
unserializeGlobals(CheckpointIn &cp)Serializablestatic
unserializeSection(CheckpointIn &cp, const char *name)Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)Serializableinline
updateClockPeriod() const Clockedinline
voltage() const Clockedinline
wakeupEventQueue(Tick when=(Tick)-1)EventManagerinline
writeOK(PacketPtr pkt)AbstractMemoryinlineprotected
~AbstractMemory()AbstractMemoryinlinevirtual
~Clocked()Clockedinlineprotectedvirtual
~Drainable()Drainableprotectedvirtual
~Serializable()Serializablevirtual
~SimObject()SimObjectvirtual

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