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tsunamireg.h
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1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * Authors: Ali Saidi
29  */
30 
35 #ifndef __TSUNAMIREG_H__
36 #define __TSUNAMIREG_H__
37 
38 #define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000)
39 
40 // CChip Registers
41 #define TSDEV_CC_CSR 0x00
42 #define TSDEV_CC_MTR 0x01
43 #define TSDEV_CC_MISC 0x02
44 
45 #define TSDEV_CC_AAR0 0x04
46 #define TSDEV_CC_AAR1 0x05
47 #define TSDEV_CC_AAR2 0x06
48 #define TSDEV_CC_AAR3 0x07
49 #define TSDEV_CC_DIM0 0x08
50 #define TSDEV_CC_DIM1 0x09
51 #define TSDEV_CC_DIR0 0x0A
52 #define TSDEV_CC_DIR1 0x0B
53 #define TSDEV_CC_DRIR 0x0C
54 #define TSDEV_CC_PRBEN 0x0D
55 #define TSDEV_CC_IIC0 0x0E
56 #define TSDEV_CC_IIC1 0x0F
57 #define TSDEV_CC_MPR0 0x10
58 #define TSDEV_CC_MPR1 0x11
59 #define TSDEV_CC_MPR2 0x12
60 #define TSDEV_CC_MPR3 0x13
61 
62 #define TSDEV_CC_DIM2 0x18
63 #define TSDEV_CC_DIM3 0x19
64 #define TSDEV_CC_DIR2 0x1A
65 #define TSDEV_CC_DIR3 0x1B
66 #define TSDEV_CC_IIC2 0x1C
67 #define TSDEV_CC_IIC3 0x1D
68 
69 // BigTsunami Registers
70 #define TSDEV_CC_BDIMS 0x1000000
71 #define TSDEV_CC_BDIRS 0x2000000
72 #define TSDEV_CC_IPIQ 0x20 //0xf01a000800
73 #define TSDEV_CC_IPIR 0x21 //0xf01a000840
74 #define TSDEV_CC_ITIR 0x22 //0xf01a000880
75 
76 
77 // PChip Registers
78 #define TSDEV_PC_WSBA0 0x00
79 #define TSDEV_PC_WSBA1 0x01
80 #define TSDEV_PC_WSBA2 0x02
81 #define TSDEV_PC_WSBA3 0x03
82 #define TSDEV_PC_WSM0 0x04
83 #define TSDEV_PC_WSM1 0x05
84 #define TSDEV_PC_WSM2 0x06
85 #define TSDEV_PC_WSM3 0x07
86 #define TSDEV_PC_TBA0 0x08
87 #define TSDEV_PC_TBA1 0x09
88 #define TSDEV_PC_TBA2 0x0A
89 #define TSDEV_PC_TBA3 0x0B
90 #define TSDEV_PC_PCTL 0x0C
91 #define TSDEV_PC_PLAT 0x0D
92 #define TSDEV_PC_RES 0x0E
93 #define TSDEV_PC_PERROR 0x0F
94 #define TSDEV_PC_PERRMASK 0x10
95 #define TSDEV_PC_PERRSET 0x11
96 #define TSDEV_PC_TLBIV 0x12
97 #define TSDEV_PC_TLBIA 0x13
98 #define TSDEV_PC_PMONCTL 0x14
99 #define TSDEV_PC_PMONCNT 0x15
100 
101 #define TSDEV_PC_SPST 0x20
102 
103 
104 // DChip Registers
105 #define TSDEV_DC_DSC 0x20
106 #define TSDEV_DC_STR 0x21
107 #define TSDEV_DC_DREV 0x22
108 #define TSDEV_DC_DSC2 0x23
109 
110 // I/O Ports
111 #define TSDEV_PIC1_MASK 0x21
112 #define TSDEV_PIC2_MASK 0xA1
113 #define TSDEV_PIC1_ISR 0x20
114 #define TSDEV_PIC2_ISR 0xA0
115 #define TSDEV_PIC1_ACK 0x20
116 #define TSDEV_PIC2_ACK 0xA0
117 #define TSDEV_DMA1_RESET 0x0D
118 #define TSDEV_DMA2_RESET 0xDA
119 #define TSDEV_DMA1_MODE 0x0B
120 #define TSDEV_DMA2_MODE 0xD6
121 #define TSDEV_DMA1_MASK 0x0A
122 #define TSDEV_DMA2_MASK 0xD4
123 #define TSDEV_CTRL_PORTB 0x61
124 #define TSDEV_TMR0_DATA 0x40
125 #define TSDEV_TMR1_DATA 0x41
126 #define TSDEV_TMR2_DATA 0x42
127 #define TSDEV_TMR_CTRL 0x43
128 #define TSDEV_KBD 0x64
129 #define TSDEV_DMA1_CMND 0x08
130 #define TSDEV_DMA1_STAT TSDEV_DMA1_CMND
131 #define TSDEV_DMA2_CMND 0xD0
132 #define TSDEV_DMA2_STAT TSDEV_DMA2_CMND
133 #define TSDEV_DMA1_MMASK 0x0F
134 #define TSDEV_DMA2_MMASK 0xDE
135 
136 /* Added for keyboard accesses */
137 #define TSDEV_KBD 0x64
138 
139 #define TSDEV_RTC_ADDR 0x70
140 #define TSDEV_RTC_DATA 0x71
141 
142 #define PCHIP_PCI0_MEMORY ULL(0x00000000000)
143 #define PCHIP_PCI0_IO ULL(0x001FC000000)
144 #define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000)
145 #define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY
146 #define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
147 
148 
149 // System Control PortB Status Bits
150 #define PORTB_SPKR_HIGH 0x20
151 
152 #endif // __TSUNAMIREG_H__

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