Section \#2: PRAM models
(CS838: Topics in parallel computing, CS1221, Thu, Jan 21, 1999, 8:00-9:15 a.m.)
- RAM model
- PRAM model
- Handling shared memory access conflicts
- Computational power
- Simulation of large PRAMs on small PRAMs
- Simulation of stronger PRAM models on weaker ones
Random Access Machine is a favorite model of a sequential computer. Its main features are:
- Computation unit with a user defined program.
- Read-only input tape and write-only output tape.
- Unbounded number of local memory cells.
- Each memory cell is capable of holding an integer of unbounded size.
- Instruction set includes operations for moving data between memory cells, comparisons and conditional branches, and simple arithmetic operations.
- Execution starts with the first instruction and ends when a HALT instruction is executed.
- All operations take unit time regardless of the lengths of operands.
- Time complexity = the number of instructions executed.
- Space complexity = the number of memory cells accessed.
Parallel Random Access Machine is a straightforward and natural generalization of RAM. It is an idealized model of a shared memory SIMD machine. Its main features are:
PRAM is an attractive and important model for designers of parallel algorithms. Why?
- Unbounded collection of numbered RAM processors P0, P1, P2,... (without tapes).
- Unbounded collection of shared memory cells M, M, M,....
- Each Pi has its own (unbounded) local memory (registers) and knows its index i.
- Each processor can access any shared memory cell (unless there is an access conflict, see further) in unit time.
- Input af a PRAM algorithm consists of n items stored in (usually the first) n shared memory cells.
- Output of a PRAM algorithm consists of n' items stored in n' shared memory cells.
- PRAM instructions execute in 3-phase cycles.
- Read (if any) from a shared memory cell.
- Local computation (if any).
- Write (if any) to a shared memory cell.
- Processors execute these 3-phase PRAM instructions synchronously.
- Special assumptions have to be made about R-R and W-W shared memory access conflicts.
- The only way processors can exchange data is by writing into and reading from memory cells.
- P0 has a special activation register specifying the maximum index of an active processor. Initially, only P0 is active, it computes the number of required active processors and loads this register, and then the other corresponding processors start executing their programs.
- Computation proceeds until P0 halts, at which time all other active processors are halted.
- Parallel time complexity = the time elapsed for P0's computation.
- Space complexity = the number of shared memory cells accessed.
- It is natural: the number of operations executed per one cycle on p processors is at most p.
- It is strong: any processor can read or write any shared memory cell in unit time.
- It is simple: it abstracts from any communication or synchronization overhead, which makes the complexity and correctness analysis of PRAM algorithms easier. Therefore,
- It can be used as a benchmark: If a problem has no feasible/efficient solution on PRAM, it has no feasible/efficient solution on any parallel machine.
- It is useful: it is an idealization of existing (and nowaday more and more abundant) shared memory parallel machines.
The PRAM corresponds intuitively to the programmers' view of a
parallel computer: it ignores lower level architectural constraints,
and details, such as memory access contention and overhead,
synchronization overhead, interconnection network throughput,
connectivity, speed limits and link bandwidths, etc.
Constrained PRAM models
Limiting the amount of PRAM shared memory corresponds to restricting the amount of information that can be communicated between processors in one step. For example, a distributed memory machine with processors interconnected by a shared bus can be modeled as a PRAM with one shared memory cell.
- Bounded number of shared memory cells. This may be called a small memory PRAM. If the input data set exceeds the capacity of the shared memory, the input and/or output values can be distributed evenly among the processors.
- Bounded size of a machine word and/or memory cell. This parameter is usually called word size of PRAM.
- Bounded number of processors. This may be called a small PRAM. If the number of threads of execution is higher, processors may interleave several threads.
- Constraints on simultaneous access to shared memory cells: handling access conflicts.
Handling shared memory access conflicts
To make the PRAM model realistic and useful, some mechanism has to be defined to resolve read and write access conflicts to the same shared memory cell.
Concurrent Read has a clear semantics, whereas Concurrent Write has to be further constrained. There exist several basic submodels:
- Exclusive Read Exclusive Write (EREW) PRAM:
No two processors are allowed to read or write the same shared memory cell simultaneously.
- Concurrent Read Exclusive Write (CREW) PRAM:
Simultaneous reads of the same memory cell are allowed, but only one processor may attempt to write to an individual cell
- Concurrent Read Concurrent Write (CRCW) PRAM:
Both simultaneous reads and both simultaneous writes of the same memory cell are allowed.
The following example demonstrates the differences among submodels.
- PRIORITY CRCW: the processors are assigned fixed distinct priorities and the processor with the highest priority is allowed to complete WRITE.
- ARBITRARY CRCW: one randomly chosen processor is allowed to complete WRITE. The algorithm may make no assumptions about which processor was chosen.
- COMMON CRCW: all processors are allowed to complete WRITE iff all the values to be written are equal. Any algorithm for this model has to make sure that this condition is satisfied. If not, the algorithm is illegal and the machine state will be undefined.
Assume p-processor PRAM, p<n. Assume that shared memory contains
n distinct items and P0 owns value x. The task is to let P0 know whether x occurs within the input array.
EREW PRAM algorithm:
- P0 broadcasts x to P1,...,Pp in log p steps using binary broadcast tree.
- All processors perform local searches, each on [ n/p] items in [ n/p] steps.
- Every processor defines a flag Found and all processors perform a parallel reduction.
T(n,p)=log p + n/p
CREW PRAM algorithm: A similar approach, but P1,...,Pp can read x simultaneously in O(1) time. But the final reduction takes O(log p) time anyway, so
T(n,p)=log p + n/p
COMMON CRCW PRAM algorithm: The final step takes now also O(1) time, those processors with the flag Found set can write simultaneously into P0's cell
Having this range of submodels, we must ask how they compare as to the ability to execute parallel algorithm. Various submodels may have different computational power.
PRAM submodel A is computationally stronger than submodel B, written A>=B, if any algorithm written for B will run unchanged on A in the same parallel time, assuming the same basic properties.
PRIORITY >= ARBITRARY >= COMMON >= CREW >= EREW
Simulation of large PRAMs on small PRAMs
Small PRAMs can simulate larger PRAMs. Even though relatively simple, the following two simulations are very useful and notoriously used.
The first result says that if we decrease the number of processors, the cost of a PRAM algorithm does not change, up to a multiplicative constant.
Assume p'<p. Any problem that can be solved on a p-processor PRAM in t steps can be solved on a p'-processor PRAM in t'=O(tp/p') steps assuming the same size of shared memory.
This result has an important consequence!!! If we develop a parallel PRAM algorithm with C(n,p)=o(SU(n)), we have automatically developed a better sequential algorithm.
- Partition p simulated processors into p' groups of size p/p' each.
- Associate each of the p' simulating processors with one of these groups.
- Each of the simulating processors simulates one step of its group of processors by:
- executing all their READ and local computation substeps first,
- executing their WRITE substeps then. \sq
Assume m'<m. Any problem that can be solved on a p-processor and m-cell PRAM in t steps can be solved on a max(p,m')-processor m'-cell PRAM in O(tm/m') steps.
- Partition m simulated shared memory cells into m' continuous segments Si of size m/m'.
- Each simulating processor P'i, 1<= i<= p, will simulate processor Pi of the original PRAM.
- Each simulating processor P'i, 1<= i<= m', stores the initial contents of Si into its local memory and will use M'[i] as an auxiliary memory cell for simulation of accesses to cells of Si.
- Simulation of one original READ operation:
each P'i, i=1,...,max(p,m') repeats for k=1,...,m/m':
- write the value of the k-th cell of Si into M'[i], i=1,...,m',
- read the value which the simulated processor Pi, i=1,...,p, would read in this simulated substep, if it appeared in the shared memory.
- The local computation substep of Pi, i=1,...,p, is simulated in one step by P'i.
- Simulation of one original WRITE operation is analogous to that of READ.
Simulation of stronger PRAM models on weaker ones
It is very useful to know efficient simulations of stronger PRAM models on weaker ones, since a stronger model is more convenient for the design of algorithms, whereas weaker models, such as EREW, are closer to real parallel computers. Since it is technologically difficult to build full massively parallel CREW or CRCW PRAM computers, it is important to understand the costs of simulating the CREW or CRCW machines on EREW. Any multiple access has to be converted into a series of exclusive accesses. The most important are simulations of the strongest PRIORITY CRCW on the weakest EREW.
Assume PRIORITY CRCW with the priority scheme based trivially on indexing: lower indexed processors have higher priority. One step of p-processor m-cell PRIORITY CRCW can be simulated by a p-processor mp-cell EREW PRAM in O(log p) steps.
- Each PRIORITY processor Pk is simulated by EREW processor P'k.
- Each shared memory cell M[i], i=1,...,m, of PRIORITY is simulated by an array of p shared memory cells M'[i,k], k=1,...,p, in the EREW PRAM. M'[i,1] plays the role of M[i]. M'[i,2],...,M'[i,p] are auxiliary cells used for resolving conflicts, initially empty, and organized as internal nodes of a complete binary tree Ti with p leaves. The height of every Ti is [log p].
- Simulation of a PRIORITY WRITE substep: Each EREW processor must find out whether it is the processor with the lowest index within the group of processors asking to write to the same cell, and if so, it must become the group winner and perform the WRITE operation. The other processors in the group will fail. This is done as follows:
- If Pk wants to write into M[i], processor P'k turns active and becomes k-th leaf of Ti. It knows whether it is the right or left child of its parent.
- Each active left processor stores its ID into the parent cell in its tree, marks it as occupied, and remains active.
- Each active right processor checks its parent cell. If this is empty, it stores its ID into it, and remains active. If it is occupied, it becomes idle (he lost).
- This is repeated log p times at further levels of the trees.
- The processor who managed to proceed to the root of Ti, becomes the winner who can write into M[i]. Processors which used Ti must then sweep down Ti in the reverse order to reset the cells M'[i,2],...,M'[i,p] to empty.
- Simulation of a PRIORITY READ substep: is similar.
- The same sweep-ups of the auxiliary trees are performed in parallel to determine the winners in the groups.
- The winners will read the values from the cells M'[*,1]
- During the cleaning sweep-down, the read value is distributed to the losers.
p=7, processors P2, P3, and P7 wish to write into M.
One step of PRIORITY CRCW with p processors and m shared memory cells can be simulated by an EREW PRAM in O(log p) steps with p processors and m+p shared memory cells.
- Each PRIORITY processor Pk is simulated by EREW processor P'k.
- Each PRIORITY cell M[i] is simulated by EREW cell M[i].
- EREW uses an auxiliary array A of p cells.
If Pk wants to access M[i], processor P'k writes pair (i,k) into A[k].
If Pk does not want to access any PRIORITY cell, processor P'k writes (0,k) into A[k].
- All p processors sort the array A into lexicographic order using (log p)-time parallel sort.
- Each P'k appends to cell A[k] a flag f:
f=0, if the first component of A[k] is either 0
or it is the same as the first component of A[k-1]
- Further steps differ for simulation of WRITE or READ.
- PRIORITY WRITE:
- Each P'k reads the triple (i,j,f) from cell A[k] and writes it into A[j].
- Each P'k reads the triple (i,k,f) from cell A[k] and writes into M[i] iff f=1.
- PRIORITY READ:
- Each P'k reads the triple (i,j,f) from cell A[k].
- If f=1, it reads value vi from M[i] and overwrites the third component in A[k]the flag f, with vi.
- In at most log p steps, this third component is then distributed in subsequent cells of A until it reaches either the end or an element with a different first component.
- Each P'k reads the triple (i,j,vi) from cell A[k] and writes it into A[j].
- Each P'k who asked for a READ reads the value vi from the triple (i,k,v) in cell A[k].
Assume p=7, m=4, and
Array A in the first three steps of simualtion:
|P1 wants to access M, |
|P2 wants to access M,|
|P3 wants to access M,|
|P4 wants to access M,|
|P5 wants to access M,|
|P6 wants to access M,|
|P7 wants to access no cell at all.|
Array A in simulation of WRITE:
|(2,1, ) || (4,2, ) || (2,3, ) || (1,4, ) || (4,5, ) || (2,6, ) || (0,7, )
|(0,7, ) || (1,4, ) || (2,1, ) || (2,3, ) || (2,6, ) || (4,2, ) || (4,5, )
|(0,7,0) || (1,4,1) || (2,1,1) || (2,3,0) || (2,6,0) || (4,2,1) || (4,5,0)
Array A in simulation of READ:
|(2,1,1) || (4,2,1) || (2,3,0) || (1,4,1) || (4,5,0) || (2,6,0) || (0,7,0)
|(0,7,0) || (1,4,v1) || (2,1,v2) || (2,3,0) || (2,6,0) || (4,2,v4) || (4,5,0)
|(0,7,0) || (1,4,v1) || (2,1,v2) || (2,3,v2) || (2,6,0) || (4,2,v4) || (4,5,v4)
|(0,7,0) || (1,4,v1) || (2,1,v2) || (2,3,v2) || (2,6,v2) || (4,2,v4) || (4,5,v4)
|(2,1,v2) || (4,2,v4) || (2,3,v2) || (1,4,v1) || (4,5,v4) || (2,6,v2) || (0,7,0)
|Any polylog-time PRAM algorithm is robust with respect to PRAM models.|
Fri Jan 23 by Pavel Tvrdik