FastSim v.1: A Fast Out-of-Order Processor Simulator

The out-of-order processor simulator, FastSim, uses two innovations to speed up simulation 8-15 times over Wisconsin SimpleScalar, with no loss in simulation accuracy. First, FastSim uses speculative direct-execution to accelerate the functional emulation of speculatively executed program code. Second, it uses a variation on memoization -- a well-known technique in programming language implementation -- to cache Microarchitecture states and their resulting simulator actions, and then "fast forward" the simulator execution the next time a cached state is encountered. Fast-forwarding accelerates simulation by an order of magnitude, while producing exactly the same, cycle-accurate result as conventional simulation.

FastSim v.1 was written in C and optimized by hand to use memoization. The Executable Editing Library (EEL) was used to implement direct execution. While amazingly fast, FastSim was difficult to implement and debug, and remains a fragile piece of code. The main reason for this was the difficulty of implementing memoization by hand in a complex micro-architecture simulator. Subsequent work (FastSim v.2) addressed this issue.

Here is a paper describing this simulator and its performance.

FastSim v.1 was developed as an experimental system to demonstrate the benifit of memoizing out-of-order simulation. There is no plan to release this software.

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