An Out-Of-Order Processor Simulator

This simulator models a detailed out-of-order micro-architecture for the SPARC-V9 instruction set. In addition to an out-of-order pipeline, this simulator models non-blocking data caches, register renaming, branch prediction, speculative execution, and other detailed features.

Below are the Facile and C source files for this simulator:

Follow this link to see the results of analyzing the simulator. The Facile compiler performs binding time analysis to determine which parts of the simulator can be skipped over by fast-forwarding. Annotated source code is generated in HTML format by the compiler to help visualize the results of its analysis.

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