An In-Order Pipeline Simulator

This simulator models a SPARC-V9 ISA with an imaginary in-order execution pipeline. Below are the Facile source files for this simulator:

Follow this link to see the results of analyzing the simulator. The Facile compiler performs binding time analysis to determine which parts of the simulator can be skipped over by fast-forwarding. Annotated source code is generated in HTML format by the compiler to help visualize the results of its analysis.

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