Yu-Chi Lai


CS Course Project Description

CS367 Introduction to Data Structures

bulletSource Code of Homework in Java

CS564 Database Management Systems: Design and Implementation

bulletP1: Buffer Manager and Hash Function
bulletP4: External Sort

CS640 Introduction to Computer Networks

bulletSimple Sender and Reciever
bulletSimple Sender, Forwarder and Reciever
bulletBroadcast method

CS755 VLSI System Designs

Final Project Abstract. The target of this project is to implement a 16-entry destination reorder buffer (DRB) that might be used in an implementation of timestamp snooping. Conceptually each message is tagged with a logical timestamp. Messages may arrive at the DRB in any order, but may only be forwarded to the device in increasing timestamp order. The primary purpose of this buffer is to reorder message that arrive out of order. It is similar to implement a priority queue. We select the method of logic priority selection from the 16-entry buffer. The entire circuit consists of the input buffer, parity checker, the input writing control logic, the output reading control logic, the token control logic, parity generator, and the output buffer. The functionality, performance, and so on are discussed in the following section.



      E-mail        yu-chil@cae.wisc.edu

      Address    422 N. Segoe Rd. Apt. 73B,

                          Madison, WI 53705

      Phone   H:           608-236-9763

                     CS:       608-262-7500