Tejaswi Agarwal Graduate student @ UW-Madison

5. Improving Soft-core OR1200 Processor Performance

Guide: Professor R. Maheshwari, Vellore Institute of Technology, Chennai, India

Independent Research Project at Vellore Institute of Technology, Chennai, India

Accepted at the Student Research Symposium, ICACCI 2013, Mysore, India

Soft-core processors are being increasingly used in various embedded applications due to their flexibility, cost effectiveness and platform independence. It enables designers to modify the core designs with ease to achieve specific application goals. In this paper, the design of an enhanced soft-core processor based on OpenCores that is suited for telecommunication, multimedia and a variety of embedded applications is presented. The OR1200 platform, which is a 32-bit DSP, with RISC Harvard micro architecture including a 5-stage integer execution pipeline, is used. We enhance the processor design to include a Global Memory Stall Controller which manages the Data Path Unit of the processor and distributes stall signals whenever the memory latency cannot be hidden. Also, we suggest improvements in the data path of the processor to enhance it for better multimedia applications. Finally, we propose to add a Hazard Controller to the execution pipeline to handle data and branch hazards.

This phase proposes a new technique of embedding multigrain parallel processing HPRC using FPGA in the CPU/DSP unit of OR1200 a soft-core RISC processor. The core performance is increased by placing a multigrain parallel processing HPRC internally in the Integer Execution Pipeline unit of the CPU/DSP core. The performance of HRPC unit inside the OR1200 soft core is achieved by dynamic hardware multitasking.Through ICAP (Internal Configuration Access port) the inter-module communication is ensured which is a reasonable medium for cross chip communication. The multigrain parallelism in HPRC is accomplished by two functions:

i)HPRC_Parallel_Start - to trigger the parallelism

ii)HPRC_Parallel_End - to stop the parallelism.

Conclusion:

We proposed modifications to the existing OR1200 architecture which would enhance its performance. It offers good flexibility and adaptability which balances computing performances and could be used as an embedded processor with multiple applications. Originally started off as a design exploration, currently we are in the stages of implementing the above modules in the OR1200 soft-core processor.

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