Technical Reference
Notice: Hayes Microcomputer Products, Inc. reserves the right to make improvements to the product described in this reference at any time and without notice.
Hayes and ESP are trademarks of Hayes Microcomputer Products, Inc. Other trademarks mentioned in this document are trademarks of their respective companies.
This document is copyrighted. All rights are reserved. This document may not, in whole or part, be copied, photocopied, reproduced, translated or reduced to any electronic medium or machine-readable form without prior consent, in writing, from Hayes Microcomputer Products, Inc.
© 1995 Hayes Microcomputer Products, Inc.
All rights reserved. Printed in U.S.A.
This document explains the operating procedures for the Hayes COM-bic's ESI interface. The COM-bic chip is an enhanced serial port bus interface chip that eliminates data loss while significantly reducing host processor overhead. These improvements are provided by the COM-bic chip's combination of 1024-byte transmit and receive first-in first-out buffers (FIFOs) with automatic software or hardware flow control. A parallel microprocessor interface is also included for onboard peripheral applications.
The COM-bic chip can be operated in 16450/550 Compatibility, Enhanced DMA, Enhanced Programmed I/O, or Enhanced Memory-mapped I/O communication modes. In Compatibility Mode, 1024-byte transmit and receive FIFOs can be enabled with the standard 16550 trigger levels for the lower 14 bytes. This configuration gives the host PC 1010 character times to service the 14 byte trigger level before data overflow can occur. In Enhanced modes, the 1024-byte receive FIFO can be enabled to reduce context switching due to interrupts up to 64 times versus conventional 16550 UARTs.
Typical applications for the COM-bic chip include high-speed multiport serial cards, board-level modems, and ISDN terminal adapters.
Adapter ID, LSB and MSB POS 2 Enhanced I/O and Memory Addresses POS 3 Arbitration Level and Enhanced Interrupt POS 4 Address and Interrupt Enable POS 5 COM Port Address and Interrupt Selection
The tables below lists all of the possible configuration options.
RAM Base Switch Settings
------------------------
Bit Description
210 Setting Memory Address
000 C0000 - C1FFF
001 C4000 - C5FFF
010 C8000 - C9FFF
011 CC000 - CDFFF
100 D0000 - D1FFF
101 D4000 - D5FFF
110 D8000 - D9FFF
111 DC000 - DDFFF
Note: The memory address decoder in the COM-bic powers up in a
disabled state and may only be enabled through the
Set Mode command (10h).
I/O Base Switch Settings
------------------------
Bit Description
43210 Setting Enhanced I/O Address (Hex)
00000 0100 - 0107
00001 0140 - 0147
00010 0180 - 0187
00011 0200 - 0207
00100 0240 - 0247
00101 0280 - 0387
00110 0300 - 0307
00111 0380 - 0387
00nnn (I/O Base) + 0000h
10nnn (I/O Base) + 4000h
01nnn (I/O Base) + 8000h
11nnn (I/O Base) + C000h
UART COMn Switch
----------------
Bit Description
10 Setting UARTEN UART I/O Address Interrupt
00 0 03F8 - 03FF COM1 4
01 0 02F8 - 02FF COM2 3
10 0 03E8 - 03EF COM3 4
11 0 02E8 - 02EF COM4 3
xx 1 disabled DD
Note: All of the options listed above may not be available on a given product.
POS Address
-----------
Bit 100h 101h 102h 103h 104h 105h
0 0 1 Card Enable Arb Lvl0 Port 1 Port 1
Addr enable Addr Sel0
1 1 1 I/O Base 0 Arb Lvl1 Port 1 Port 1
IRQ enable Addr Sel1
2 1 1 I/O Base 1 Arb Lvl2 Port 2 Port 1
Addr enable IRQ Sel
3 0 1 I/O Base 2 Arb Lvl3 Port 2
IRQ enable Port 2
Addr Sel0
4 0 0 RAM Base 0 Enh IRQ 0 Enh IRQ Port 2
(A13) Enable Addr Sel1
5 0 1 RAM Base 1 Enh IRQ 1 I/O Addr Port 2
A(14) Enable IRQ Sel
6 0 1 RAM Base 2 Enh IRQ 2 RAM Addr N/A
A(15) Enable
7 0 0 RAM Base 3 Enh IRQ 3 N/A N/A
A(16)
100h = Adapter ID (LSB)
101h = Adapter ID (MSB)
106, 107h are not used.
Bit Description
7-0 Adapter ID (MSB)
6F hex
Bit Description
7-0 Adapter ID (LSB)
06 hex
Bit Description
7654 RAM Base Setting Memory Address (4K Block, 4 port max)
0000 C0000 - C0FFF
0001 C2000 - C2FFF
0010 C4000 - C4FFF
0011 C6000 - C6FFF
0100 C8000 - C8FFF
0101 CA000 - CAFFF
0110 CC000 - CCFFF
0111 CE000 - CEFFF
1000 D0000 - D0FFF
1001 D2000 - D2FFF
1010 D4000 - D4FFF
1011 D6000 - D6FFF
1100 D8000 - D8FFF
1101 DA000 - DAFFF
1110 DC000 - DCFFF
1111 DE000 - DEFFF
321 I/O Base Setting I/O Address (32byte Block 4 port max)
000 8100 - 811F
001 8140 - 815F
010 8180 - 819F
011 8200 - 821F
100 8240 - 825F
101 8280 - 829F
110 8300 - 831F
111 8380 - 839F
0 Card Enable
Bit Description
7654 Enhanced IRQ Setting IRQ
0000 disabled
0001 disabled
0010 9
0011 3
0100 4
0101 5
0110 disabled
0111 disabled
1000 disabled
1001 disabled
1010 10
1011 11
1100 12
1101 shared IRQ*
1110 14
1111 15
3210 Arbitration Level Setting DMA Arbitration Level
0000 0
1110 14
1111 not used
Bit Description 0 Port 1 Address enable 1 Port 1 IRQ enable 2 Port 2 Address enable 3 Port 2 IRQ enable 4 Enhanced IRQ Enable 5 I/O Address Enable 6 RAM Address Enable 7 Not usedNote: Port 2 refers to the first slave port on a multiport card.
Bit Description
7 N/A
6 N/A
5 Port 2 IRQ Select Setting UART Interrupt
1 3
0 4
4,3 Port 2 Address Select Setting UART I/O Address
00 03F8 - 03FF COM1
01 02F8 - 02FF COM2
10 3220 - 3227 COM3
11 3228 - 322F COM4
2 Port 1 IRQ Select Setting UART Interrupt
1 3
0 4
1,0 Port 1 Address Select Setting UART I/O Address
00 03F8 - 03FF COM1
01 02F8 - 02FF COM2
10 3220 - 3227 COM3
11 3228 - 322F COM4
Note: Port 2 refers to the first slave port on a multiport card.
In Compatibility Mode the COM-bic chip can be operated by an existing application using a standard serial communication driver. Compatibility Mode allows the COM-bic chip to function like a standard serial port with or without a 1024-byte buffer and hardware flow control.
Enhanced mode allows the COM-bic to conduct 8- or 16-bit data transfers with 1024-byte FIFOs and automatic flow control. This combination provides full data integrity at high communication speeds, even in multitasking environments.
All ESI commands are issued by writes to the CMD1 and CMD2 registers. The CMD1 and CMD2 registers reside at I/O base address +4 and I/O base address +5 and only affect their assigned individual ports. Status information is obtained by reading the CMD1 and CMD2 registers and is referred to as STAT1 or STAT2. Below is a summary of the enhanced register set that exists for each port in the system.
Enhanced Register Address Register Ready I/O Base +0 Service ID I/O Base +1 Data Read / Write I/O Base +2 STAT1 / CMD1 I/O Base +4 STAT2 / CMD2 I/O Base +5 Receive Word Status I/O Base +7
For further information on the enhanced register set, see ESI Enhanced Register Set.
The following chart shows the relationship between various features and operating modes.
Feature Compat. Mode Enhanced Mode ------------------------------------------------------------ Standard UART access COM1-4 Y disabled Automatic hardware flow control Y Y Automatic software flow control disabled* Y 8/16-bit programmed I/O Y Y 8/16-bit memory-mapped I/O Y Y 8-bit DMA disabled Y * planned for later release
Note: Any combination of the above features can be enabled at the same time.
Note: Do not set the master port to IRQ 13 or the enhanced IRQs will not reach the host bus.
| DMA Circuitry
|
|
|
| Error Status Mask
| (Get Error Status CMD12h)
|
| | Start Tx Break
| | Flow Off Timeout S
| | UART Modem Status T
| | Rx Break A
| | Rx Framing Error T
| DMA Timeout <------| | Rx Parity Error 1
| DMA TC <-----------| | Rx FIFO Overflow
Host | | Rx Timeout
Enhanced <--| Error Status <---------|
IRQ | | Remote Tx Flow On S
| Tx Level Reached <-| | Local Tx Flow On T
| Rx Level Reached <-| | Local Tx Flow Off A
| | Remote Tx Flow Off T
| 2
|
|
|
| Rx/Tx FIFOs
Note: The Tx and Rx Level Reached register bits are cleared when the
FIFO level goes below a user-specified value. All other bits are
cleared after their associated registers have been read.
Note: All 16-bit (word) transfers should be made on even address locations, and wait state should be enabled with the Set UART Clock Prescaler Command (23h).
When multiple COM-bic ports are cascaded on a single board, the slave ports derive their I/O addresses from the master port as follows:
I/O addr +8 +16 +24 +32 +40 +48 +56 ------------------------------------------------------------ | | | | | | | | | | Master |Slave1|Slave2|Slave3|Slave4|Slave5|Slave6|Slave7| | | | | | | | | | ------------------------------------------------------------
Note: The master port and all slave ports have individual enhanced register sets.
Note: The Receive Timeout may also be used to get the remaining bytes left in the buffer after the last transfer. See the Set Error Status Mask (07h) and Get Error Status (12h) commands for more information.
Once memory-mapped operation is enabled, any read or write in the 1K RAM space reserved for the port will be directly mapped to the receive or transmit FIFO.
Note: All 16-bit (word) transfers should be made on even address locations, and wait state should be enabled with the Set UART Clock Prescaler (23h) Command.
In a multiport application, slave port memory address blocks are decoded as follows:
+1K +2K +3K +4K +5K +6K +7K
| | | | | | | |
--------------------------------------------------------
| | | | | | | | |
|Master|Slave1|Slave2|Slave3|Slave4|Slave5|Slave6|Slave7|
| | | | | | | | |
--------------------------------------------------------
addr D000- D0400- D0800- D0C00- D1000- D1400- D1800- D1C00-
ex. D03FF D07FF D08FF D0FFF D13FF D17FF D18FF D1FFF
Note: Memory-mapped operation must be enabled on the master port to
allow memory-mapped slave port operation.
Note: The Receive Timeout may also be used to get the remaining bytes left in the buffer after the last transfer. See the Set Error Status Mask (07h) and Get Error Status (12h) commands for more information.
If enabled, the COM-bic will generate a Service Request after the byte containing a Parity Error, Framing Error, or Break Interrupt condition was transferred to the host, and the DMA transfer will be halted. Otherwise, the COM-bic will issue a DMA Terminal Count service request when the transfer is finished, or a DMA Timeout service request if the DMA transfer halted for some other reason.
Since a COM-bic chip will not typically respond to new host commands while conducting a DMA transfer, a host interrupt service routine should usually enable DMA transfers as the last operation done on that interrupt.
Receive DMA command issued
|
|
|
Start DMA <--------------------------------------|
| |
| |
| |
COM-bic asserts DMA request |
| |
|<-------------------------------------| |
| | |
DMA acknowledge from host --N--> DMA Timeout --N--| |
| Reached? |
Y | |
| Y |
| | |
COM-bic immediately Set DMA timeout bit |
deasserts DMA request in SID registers |
| | |
| | |
| | |
Transfer byte I/O to memory Exit |
| |
| |
| |
Error byte received? --N--> Terminal Count Reached? --N--|
| |
| Y
| |
Y Set TC bit in SID register
| |
| |
| Exit
See error status bit(s)
|
|
|
Exit
Transmit DMA
command issued
|
|<------------------------------------------------------
| |
Start DMA |
| |
| |
| |
COM-bic asserts DMA request |
| |
|<-----------------------------------------------| |
| | |
DMA acknowledge from host? --N--> DMA timeout --N-->--| |
| reached? |
Y | |
| Y |
| | |
COM-bic immediately Set DMA timeout |
deasserts DMA request bit in SID registers |
| | |
| | |
| | |
Byte transfer memory to I/O Exit |
| |
| |
| |
Terminal count reached? --N-->------------------------------
|
Y
|
COM-bic sets TC bit
in SID register
|
|
|
Exit
The COM-bic chip will transmit a maximum of 1 character after it receives a flowoff signal. If the COM-bic chip is flowed off for longer than the Flow Off Timeout time, it will issue a Flowed Off Timeout Error Status service request.
When the COM-bic chip's receive FIFO reaches the flow off point it will deassert RTS. When the receive FIFO drops to the flow on point, the COM-bic chip will assert RTS.
Note: The RTS bit must be set in the UART's modem control register by either a direct write or a "Write to UART Register" (0Eh) command.
When the COM-bic chip's receive FIFO reaches the flow off point, it will deassert DTR. When the receive FIFO drops to the flow on point, the COM-bic chip will assert DTR.
Note: The DTR bit must be set in the UART's modem control register by either a direct write or a "Write to UART Register" (0Eh) command.
Note: The XON and XOFF characters are programmable. The parity bit of received XON/XOFF characters may be programmed to be compared or ignored.
When the COM-bic chip's receive FIFO reaches the flow off point it will send an XOFF character. When the receive FIFO drops to the flow on point the COM-bic chip will send an XON character.
The XON or XOFF character will be sent whether or not the transmitter is flowed off.
The COM-bic receiver sending a flow character will not cause the COM-bic's transmitter to flow off.
Transmit -------- Action Data Transmitted To send DLE data DLE, DLE XOR'ed with 21 hex To send DC1 data DLE, DC1 XOR'ed with 21 hex To send DC3 data DLE, DC3 XOR'ed with 21 hex To XON transmitter DC1 To XOFF transmitter DC3
Receive ------- Data Received Action DLE, XXX XXX XOR'ed with 21 hex sent to host DC1 XOFFDstop transmitting DC3 XONDstart transmitting
The DLE, DC1, DC3, and hex 21 characters are compatible with Hayes communications products, but they may be reprogrammed to other characters.
The parity bit of received DLE, DC1, or DC3 characters and characters recognized as DLE, DC1, or DC3 for transmitter quoting (those characters in the DLE - XOR sequence) may be programmed to be compared or ignored. The same characters are used for transmit and receive flow control.
General Commands: CMD 1 Subsequent Reads/Writes ------------------------------------------------------------ Reset 00 Get self test results 01 STAT1 STAT2 (HW stat) Get comp. mode 02 STAT1 (Sw set) address DIP switches Not used 03
Setup Commands CMD 1 Subsequent Reads/Writes
------------------------------------------------------------
Set enh. IRQ/DMA lvl 04 CMD2 (IRQ/DMA)
Set DMA timeout 05 CMD2 (timeout)
Set IRQ mask 06 CMD2 (IRQ mask)
Set error status mask 07 CMD2 (UART)
CMD2 (flow ctrl)
Set flow control** 08 CMD2 (Sw/Hw)
CMD2 (DSR/CTS)
Set flow cntrl char 09 CMD2 (XON)
CMD2 (XOFF)
CMD2 (escape)
CMD2 (XOR)
CMD2 (pmask)
Set rcv FIFO flow cntrl lvls 0A CMD2 (MSB flow off)
CMD2 (LSB flow off)
CMD2 (MSB on)
CMD2 (LSB on)
Set FIFO trigger lvls 0B CMD2 (MSB Rx)
CMD2 (LSB Rx)
CMD2 (MSB Tx)
CMD2 (LSB Tx)
Set rcv char timeout (ms) 0C CMD2 (timeout)
Set flow off timeout (sec) 0D CMD2 (timeout)
Set mode 10 CMD2 (UART/Enh)
Set enhanced IRQ* 1F CMD2 (Enh IRQ)
Set re-interrupt timeout* 20 CMD2 (timeout)
Set UART clock prescaler* 23 CMD2 (scale)
* new command
** function(s) changed
Operating Commands CMD 1 Subsequent Reads/Writes
------------------------------------------------------------
Reserved 11
Get error status 12 STAT1 (LSR)
STAT2 (flow event)
Get rcv bytes available 14 STAT1 (MSB) STAT2 (LSB)
Get transmit space avail 15 STAT1 (MSB) STAT2 (LSB)
Initiate DMA receive 16
Initiate DMA transmit 17
Flow off local transmitter 18
Flow on local transmitter 19
Issue line break** 1A CMD2 (state)
Flush receive FIFO 1B
Flush transmit FIFO 1C
Get mode 1E STAT1 (default = 00h)
STAT2 (current setting)
Get service ID mask* 21 STAT1 (stat)
Get receive error count* 22 STAT1 (error count MSB)
STAT2 (error count LSB)
UART Commands CMD 1 Subsequent Reads/Writes
------------------------------------------------------------
Write to UART register 0E CMD2 (address)
CMD2 (data written)
Read from UART register 0F CMD2 (address)
STAT1 (data read)
Get UART status 13 STAT1 (LSR)
STAT2 (MSR)
Set UART baud rate 1D CMD2 (div MSB)
CMD2 (div LSB)
* new command
** function(s) changed
In Compatibility Mode, the Set Mode (10h) command may be used to enable or disable the UART FIFO or hardware flow control.
In Enhanced Mode, the commands and statuses are used to transfer all information except received and transmitted serial data. Commands always use the CMD1 register. If more than one byte of additional data is required, the bytes are written sequentially to the CMD2 register, although CMD1 must be written before the first CMD2. Statuses always use the STAT1 register, and statuses that require 2 bytes use STAT1 and STAT2. Statuses returning a 16-bit numerical value use STAT1 as the most significant byte (MSB) and STAT2 as the least significant byte (LSB).
Although the COM-bic chip can only operate on one command at a time, commands may be given while serial data are being transmitted and received or a serial line break is being issued. Do not issue commands while a previous COM-bic chip DMA transfer is in progress.
Some commands require the host to download multiple bytes to CMD2. If the host issues a second command to CMD1 before transmitting all data for the first command, the COM-bic chip will abort the first command and the second command will be executed. The aborted command will not change the previous CMD2 values for the remaining data.
CMD1 = 00 hexThis command causes the COM-bic chip to flush all FIFOs, zero all setup parameters, reset the COM-bic chip I/O registers, and restore the UART registers to their hardware reset state.
The Reset command should be issued whenever the COM-bic chip has been left in an unknown state, such as following a warm boot while the COM-bic chip was in operation.
Note: Reset would not typically be issued in normal operation.
CMD1 = 01 hex STAT1 = always 00 hex STAT2 = 1 byte defined below
Previously, bits 0, 1, and 2 reflected RAM and ROM self tests. However, since the COM-bic chip does not need a microprocessor, all testing is done in the factory. This command is included for compatibility with ESI version 1.0.
STAT2
Bit Description
7 Master/Slave bit
0 = master
1 = slave
654 Hardware Type (used to identify versions)
010
3 Bus select
0 = AT bus
1 = PS/2 MCA bus
2 Self test result
0 (Always)
1 Self test result
0 (Always)
0 Self test result
0 (Always)
CMD1 = 02 hex STAT1 = 1 byte defined below
This command causes the COM-bic chip to write the DIP switches pertaining to the compatibility mode addresses to STAT1:
STAT1:
Bit Description
7 1 for ports capable of 16450/550 compatibility
0 for enhanced-only slave ports
6 always 0
5 same as bit 1
4 same as bit 0
3 always 0
2 always 0
10 COM-bic chip COM port selection:
00 COM1
01 COM2
10 COM3
11 COM4
Note: Bits 0 and 1 will always be the same as bits 4 and 5
respectively which indicates a single port COM-bic chip to
applications written for ESI v1.0.
CMD1 = 04 hex CMD2 = 1 byte defined below
This command specifies if an interrupt is issued by a service request. On the PS/2, interrupts will not be issued unless enabled both here and through the POS registers.
With an AT, this command specifies the enhanced mode interrupt request line and the DMA arbitration level. With a PS/2, the interrupt request line and the DMA arbitration level are set in POS registers and are not affected by this command.
The interrupt used in Enhanced Mode is independent of the interrupt used in compatibility mode (the same interrupt may or may not be used for both modes), and is not affected by the state of the UART Out2 register.
CMD2
----
Bit Description
7 x (Ignored)
6 x (Ignored)
54 00 = DMA disabled (affects AT only)
10 = use DMA channel 1 (affects AT only)
11 = use DMA channel 3 (affects AT only)
3 x (Ignored)
21 00 = use IRQ9 or IRQ2 for XT bus (affects AT only)
01 = use IRQ3 (affects AT only)
10 = use IRQ4 (affects AT only)
11 = use IRQ5 (affects AT only)
0 0 = interrupts disabled
1 = enabled
Note: Further enhanced IRQ options are available with the Set Enhanced IRQ (1Fh) command.
CMD1 = 05 hex CMD2 = timeout valueThis command sets the DMA Timeout value. If the time between two character DMA transfers equals the set DMA timeout value, the COM-bic chip will stop the transfer and issue a DMA Timeout service request. Allowable values are 2 to 255 clock ticks, where 1 clock tick = 10 milliseconds. A value of 0 disables the DMA timeout.
CMD1 = 06 hex CMD2 = 1 byte defined below
This command specifies the conditions which will cause the COM-bic chip to issue a service request.
CMD2 specifies which conditions will set the corresponding bit in the Service ID register. When the conditions occur, an interrupt will be generated if interrupts are enabled. A 1 enables the service request on the condition and a 0 disables the request.
CMD2 ---- Bit Description 7 DMA Timeout 6 x (Ignored)* 5 x (Ignored)* 4 x (Ignored)* 3 DMA Terminal Count IRQ enable 2 Error Status 1 Tx FIFO level reached 0 Rx FIFO level reached * Bits 4, 5, and 6 were previously used by port 2.
CMD1 = 07 hex CMD2 = 2 bytes defined below
CMD2 bytes 1 and 2 specify conditions which will generate an Error Status service request. The enabled conditions will set the Error Status bit in the Service ID register and generate an interrupt if interrupts are enabled and if the corresponding Error Status service request bit is set.
The Parity Error, Framing Error, and Break Interrupt bits also mask the status returned in response to a Get Error Status command (12h). The other bits do not affect the status returned by the Get Error Status command.
Where a "1" enables the service request on the condition and a "0" disables the request, the CMD2 format is:
CMD2
----
Byte Bit Description
1 7 Start Tx break1
6 Flowed Off Timeout
5 UART Status
4 Break Interrupt
3 Framing Error
2 Parity Error
1 Receive FIFO Overflow
0 Receive Character Timeout
2 7 x (Ignored)
6 x (Ignored)
5 x (Ignored)
4 x (Ignored)
3 Remote Tx flow On2
2 Local Tx Flowed On
1 Local Tx Flowed Off
0 Remote Tx Flowed Off
1 Previously indicated finished Tx break. See the Issue Line Break (1Ah) Commandfor further information.
2 Previously reserved.
See the Get Error Status (12h)command for status definitions.
CMD1 = 08 hex CMD2 = 2 bytes defined below
This command causes flow control to be enabled as specified by CMD2. Except for transparent XON/XOFF, transmit and receive flow control may use different flow control types, and all other flow control types may be enabled simultaneously for transmission, reception, or both.
Note: The first byte written to CMD1 no longer supports the UART loopback, set DTR, and set RTS functions (bits 4, 5, and 6) which are all available with the Write to UART Register (0Eh) command.
CMD2
----
Byte Bit Description
1 7 1 = local transmitter responds to XON/XOFF flow
control
6 x (Ignored)
5 x (Ignored)
4 x (Ignored)
3 1 = local Rx sends DTR flow control
2 1 = local Rx sends RTS flow control
1 1 = transmitter & receiver use Trans. XON/XOFF
0 1 = local receiver sends XON/XOFF flow control
2 7 x (Ignored)
6 x (Ignored)
5 1 = local transmitter responds to DSR flow contrl
4 1 = local transmitter responds to CTS flow contrl
3 x (Ignored)
2 x (Ignored)
1 x (Ignored)
0 x (Ignored)
CMD1 = 09 hex CMD2 = 5 bytes defined below
This command defines the flow control characters used by XON/XOFF and transparent XON/XOFF flow control. This command also specifies if the parity bit or most significant bit (MSB) is to be included when comparing for XON, XOFF, or DLE characters in the received data or for transparent transmit quoting. When using 8-bit plus parity transmissions, parity is always ignored for this comparison.
CMD2
----
Byte Description
5 Parity Mask. Only bits set to 1 are used in the control
character comparisons. This mask has no affect on the
received data returned to the host.
Typical values are:
FF hex - use the parity bit.
7F hex - ignore the parity bit with 7 bit serial data
or ignore the MSB with 8-bit data. For
compatibility with existing protocols, this
value is suggested for 7- or 8-bit data
regardless of the parity setting.
3F hex - ignore the parity bit with 6 bit serial data.
1F hex - ignore the parity bit with 5 bit serial data.
4 XOR character used by transparent flow. The typical
value is 21 hex.
3 Escape character used by transparent flow. The typical
value is DLE = 10 hex.
2 XOFF character. The typical value is DC3 = 13 hex.
1 XON character. The typical value is DC1 = 11 hex.
CMD1 = 0A hex CMD2 = 4 bytes defined below
This command defines the receive FIFO trigger levels which cause the COM-bic chip to assert and deassert flow control.
CMD2
----
Byte Description
4 (LSB) The receive FIFO flow on level. When the receive
3 (MSB) FIFO drops below this number of characters, the
COM-bic chip will issue the selected flow on signal
to the remote transmitter. Allowable values are 1 to
1023, must be less than the receive FIFO flow off
level, and should normally be greater than or equal
to the receive FIFO service request trigger level.
2 (LSB) The receive FIFO flow off level. When the receive
1 (MSB) FIFO reaches this number of characters, the COM-bic
chip will issue the selected flow off signal to the
remote transmitter. Allowable values are 1 to 1023,
and should normally be greater than the receive FIFO
service request trigger level.
CMD1 = 0B hex CMD2 = 4 bytes defined below
This command defines the FIFO trigger levels which will cause the COM-bic chip to generate a service request.
CMD2
----
Byte Description
4 (LSB) The transmit FIFO service request trigger level.
3 (MSB) When the transmit FIFO contains space for this many
additional characters, the COM-bic chip will issue a
Tx FIFO level reached service request. When the
transmit FIFO is filled so that this much space no
longer remains, the COM-bic chip will withdraw the
request. Allowable values are 1 to 1023.
2 (LSB) The receive FIFO service request trigger level. When
1 (MSB) the receive FIFO reaches this number of characters,
the COM-bic chip will issue an Rx FIFO level reached
service request. When the receive FIFO is emptied
below this level, the COM-bic chip will withdraw the
request. Allow able values are 1 to 1023.
CMD1 = 0C hex CMD2 = timeout value in milliseconds
This command sets the Receive Character Timeout. If there are characters in the receive FIFO or receive register and a period of time equal to the Receive Character Timeout has elapsed since the receipt of the last serial character or transmission of the last character to the host, the COM-bic chip will issue a Receive Character Timeout Error Status service request. Allowable values are 2 to 255 milliseconds, and a value of 0 disables the receive character timeout.
Note: A value of 1 may cause unwarranted Rx timeout service requests.
An Rx timeout occurring just before a DMA transfer will be masked by the DMA transfer until the transmission is completed. If the transfer emptied the Rx FIFO, a Rx Timeout Service Request may be received when there are no receive bytes available.
CMD1 = 0D hex CMD2 = timeout value in secondsThis command Sets the Flowed Off Timeout. If the COM-bic chip transmitter is flowed off by the remote receiver and not flowed back on within the Flowed Off Timeout, the COM-bic chip will set the Flowed Off Timeout error status and issue an Error Status service request. Allowable values are 2 to 255 seconds, and a value of 0 disables the timer.
CMD1 = 10 hex CMD2 = 1 byte defined below
This command causes the port to enter the mode specified by CMD2. If the Set Mode command (10h) is never issued, the COM-bic chip defaults to compatibility mode with the UART FIFO, RTS flow, and DTR flow set to 0.
CMD2
----
Bit Description
7 Compatibility Mode Trigger Level Select*
0 = normal 16550 trigger levels (1, 4, 8, 14)
1 = scaled trigger levels (1, 64, 256 512)
6 Enable Memory-mapped I/O*
0 = disabled
1 = enabled
5 Transmit DMA
0 = disabled
1 = enabled
4 Receive DMA
0 = disabled
1 = enabled
3 Compatibility Mode DTR Hardware Flow Control
0 = disabled
1 = enabled
2 Compatibility Mode RTS Hardware Flow Control
0 = disabled
1 = enabled
1 Compatibility Mode UART FIFO
0 = disabled
1 = enabled
0 Operating Mode Select
0 = compatibility mode
1 = enhanced mode
* these bits were previously reserved.
Note: Since 0 (disabled) is the specified value for this reserved bit in the previous ESI, it should not pose any compatibility problems with older software drivers.
The Compatibility Mode UART FIFO must be enabled if compatibility mode RTS or DTR flow is enabled. Bits 1, 2, and 3 are ignored if bit 0 = 1. Bits 4 and 5 are ignored if bit 0 = 0.
CMD1 = 1F hex CMD2 = 1 byte defined below
This command uses the lower four bits of the value written to CMD2 to set the enhanced IRQ. This command should be issued after interrupts have been enabled with the Set Enhanced Mode Interrupt and DMA Level (04h) command. The possible settings are as follows:
CMD2 Enhanced Interrupt 02h IRQ9 03h IRQ3 04h IRQ4 05h IRQ5 07h IRQ7 0Ah IRQ10 0Bh IRQ11 0Ch IRQ12 0Dh Shared IRQ (slave ports only) 0Eh IRQ14 0Fh IRQ15
CMD1 = 20 hex
This new command allows the host to be re-interrupted if all of the outstanding service conditions were not satisfied within a programmable interval after a read to the Service ID Register. This command uses the value written to CMD2 to set the number of 100 microsecond clock ticks from 2-255. The default value of 00h disables this function.
Note: This command is only available in AT bus mode where interrupts are edge-triggered.
CMD1 = 23h CMD2 = 1 byte defined below
This command allows the UART master clock to be multiplied up to 8 times to yield a maximum bit/s rate of 921.6 Kbps.
CMD2
----
Bit Description
7 x (Ignored)
6 x (Ignored)
5 x (Ignored)
4 x (Ignored)
3 x (Ignored)
2 1 = enable wait states (AT bus only)*
1,0 Setting Multiplier UART Clock . Max Bit/s Rate
00 x1 1.8432 MHz 115.2 Kbps
01 x2 3.6864 MHz 230.4 Kbps
10 x4 7.3728 MHz 460.8 Kbps
11 x8 14.7456 MHz 921.6 Kbps
* Bit 2 should be enabled for 16-bit (word) data transfers in AT bus
mode. This bit is ignored in PS/2 mode.
CMD1 = 11 hex
Previously, this command caused the COM-bic chip to clear the DMA Terminal Count and DMA Timeout Service Requests. Since these interrupts are now cleared immediately after a read to the Enhanced Service ID Register (I/O base +1), this command is no longer supported.
CMD1 = 12 hex STAT1 = 1 byte defined below
This command causes the COM-bic chip to map the Error Status to the Status registers and withdraw the Error Status Service Request. This command would normally be issued after the COM-bic chip has issued an Error Status service request.
Where a "1" indicates the condition is true, the Status registers will return:
STAT1 ----- Bit Name 7 Start Transmitting Break* 6 Flowed Off Timeout 5 UART Status 4 Break Interrupt 3 Framing Error 2 Parity Error 1 Receive FIFO Overflow 0 Receive Character Timeout * Previously finished transmitting break.
STAT2 ----- Bit Name 7 Not used (always 0) 6 Not used (always 0) 5 Not used (always 0) 4 Not used (always 0) 3 Remote Tx Flowed On* 2 Local Tx Flowed On 1 Local Tx Flowed Off 0 Remote Tx Flowed Off * previously unused.
Descriptions of each bit name follow:
Note: All bits are cleared upon completion of the Get Error Status command (12h).
CMD1 = 14 hex
This command causes the COM-bic chip to write the number of received bytes available in the receive FIFO buffer to the Status registers. The count does not include the byte in the Rx register, if present. STAT1 will contain the MSB and STAT2 will contain the LSB of the number of bytes available.
CMD1 = 15 hex
This command causes the COM-bic chip to write the number of bytes of space available in the transmit FIFO buffer to the Status registers. STAT1 will contain the MSB and STAT2 will contain the LSB of the number of bytes of space.
CMD1 = 16 hex
This command causes the COM-bic chip to begin transferring data from the receive FIFO to the system DMA controller through the DMA Rx register if the system DMA controller was previously set up for the transfer to occur. This command also causes the COM-bic chip to temporarily suspend all pending service requests, postpone issuing new service requests until the DMA transfer halts, and withdraw the DMA Terminal Count Reached and DMA Timeout service requests.
When the number of bytes transferred equals the transfer count specified to the system DMA controller, the transfer halts and a DMA Terminal Count service request will be issued. If too much time elapses between transferred characters, the transfer will halt and a DMA Timeout service request will be issued. If a byte associated with a stored Parity Error, Framing Error, or Break Interrupt status is transferred to the host, the transfer will halt and a Status Error service request will be issued.
CMD1 = 17 hex
This command causes the COM-bic chip to begin transferring data from the system DMA controller to the transmit FIFO through the DMA Tx register. The system DMA controller must have been previously set up for the transfer to occur. This command also causes the COM-bic chip to temporarily suspend all pending service requests, postpone issuing new service requests until the DMA transfer halts, and withdraw the DMA Terminal Count and DMA Timeout service requests.
When the number of bytes transferred equals the transfer count specified to the system DMA controller, the transfer halts and a DMA Terminal Count service request will be issued. If too much time elapses between transferred characters, the transfer will halt and a DMA Timeout service request will be issued.
CMD1 = 18 hex
This command causes the COM-bic chip to cease transmitting, regardless of what flow control is enabled or active. It then sets the Local Tx Flowed Off status bit and issues a Status Error Service Request if this bit is enabled.
Transmission will resume if the Flow On Local Transmitter command (18h) is issued or if XON is enabled and an XON character is received. CTS or DSR will not cause transmission to resume.
CMD1 = 19 hex
This command causes the COM-bic chip to resume transmitting if it had ceased because of an XOFF or a Flow Off Local Transmitter command and then clears the Local Tx Flowed Off status bit. Transmission will not resume if the COM-bic chip is flowed off because of CTS or DSR.
CMD1 = 1A hex CMD2 = set/clear break
CMD2
----
Bit Description
7-1 x (Ignored)
0 0 = clear break
1 = set break
Previously, this command started a programmable length break generator to IRQ the host upon completion of the break. It now gives application software direct control over the break operation by generating an enhanced interrupt when the break actually starts. The break is synchronized to wait until the Tx buffer is empty and the last character frame has cleared the UART transmitter shift register. The application software may then accurately control the length of the break.
Note: This command cannot be used in Compatibility Mode, but it may be used with any FIFO enabled mode of operation.
CMD1 = 1B hex
This command causes the COM-bic chip to flush all data in the receive FIFO.
CMD1 = 1C hex
This command causes the COM-bic chip to flush all data in the transmit FIFO.
CMD1 = 1E hex STAT1 = 1 byte defined below STAT2 = 1 byte defined below
This command causes the COM-bic chip to write the power-up default mode to STAT1 and the currently selected mode to STAT2.
For this command the default mode in STAT1 will always be 00h to indicate compatibility mode.
The value in STAT2 will reflect the additional memory-mapped I/O and scaled threshold enable bits from the Set Mode (10h) command and the normal values for the current mode.
STAT1 ----- Bit Description 7 - 0 Always 00h
STAT2
-----
Bit Description
7 Compatibility Mode Trigger Levels
0 = Normal 16550 trigger levels (2, 4, 8, 14)
1 = scaled trigger levels (1, 64, 256, 512)
6 Enable Memory-mapped I/O Enable
0 = disabled
1 = enabled
5 Enhanced Mode Tx Transfer Type Select
0 = programmed I/O mode
1 = DMA mode
4 Enhanced Mode Rx Transfer Type Select
0 = programmed I/O mode
1 = DMA mode
3 Compatibility Mode DTR Hardware Flow Enable
0 = disabled
1 = enabled
2 Compatibility Mode RTS Hardware Flow Enable
0 = disabled
1 = enabled
1 Compatibility Mode UART FIFO Enable
0 = disabled
1 = enabled
0 Operating Mode Select
0 = compatibility mode
1 = enhanced mode
CMD1 = 21 hex STAT1 = 1 byte defined below
This command remaps STAT1 to reflect the current state of the service ID mask with the following bit assignments.
STAT1 ----- Bit Interrupt 7 1 = DMA timeout IRQ enable 6 0 (Always) 5 0 (Always) 4 0 (Always) 3 1 = DMA TC IRQ enable 2 1 = Error Status IRQ enable 1 1= Tx FIFO level IRQ enable 0 1= Rx FIFO level IRQ enable
CMD1 = 22 hex STAT1 = error count MSB STAT2 = error count LSB
This command returns the number of bytes in the receive FIFO that have parity, framing, or break interrupt errors and remaps STAT1 to contain the most significant byte (MSB) and STAT2 to contain the least significant byte (LSB) of this value.
Note: The value is latched internally upon the issuance of this command and is not released for update until after STAT2 is read or another command is written to CMD1.
CMD1 = 0E hex CMD2 = 2 bytes defined below
This command writes the specified byte to the specified UART register.
The Interrupt Enable, FIFO Control, Line Control, and Modem Control UART Registers may be accessed with this command.
CMD2 ---- Byte Description 2 Data to be written to the UART register 1 UART register 00 - 07 hex
CMD1 = 0F hex CMD2 = the selected UART register, 00 hex to 07 hex. STAT1 = the value returned from the UART register.
This command reads the specified UART register and returns the byte read in STAT1. The host may use this command to read any of the UART registers.
Note: When enhanced mode is selected (or the port is an enhanced-only slave) the UART is not directly accessible through the compatibility mode address and must be manipulated with this command and the Write to UART (0Eh), Set UART Baud (1Dh), and Get UART Status (13h) commands.
CMD1 = 13 hex
This command causes the COM-bic chip to write the current state of the UART Line Status Register and UART Modem Status Register to the STAT1 and STAT2 registers, respectively. The host should use the Get UART Status command in enhanced mode instead of reading the LSR or MSR from the UART.
CMD1 = 1D hex CMD2 = 2 bytes defined below
This command sets the UART baud rate. The command may cause the loss of some serial data if it is issued while data are being received or transmitted.
CMD2 ---- Byte Description 2 (LSB) The UART Divisor Latch. The divisor latch value = 1 (MSB) 115200 divided by the baud rate.
Note: The clock prescaler can be used to multiply by 1x, 2x, 4x, or 8x.
Register Ready Service ID Rx1 Receive Data Tx1 Transmit Data Rx2 Receive Data for Port 2 Tx2 Transmit Data from Port 2 STAT1 CMD1 STAT2 CMD2 DMA Rx DMA Tx Received Word Status
Register R/W Address Register Ready Read Enhanced base + 0 Service ID Read Enhanced base + 1 Rx1 Read Enhanced base + 2 Tx1 Write Enhanced base + 2 Not Used (Rx2) Read Enhanced base + 3 Not Used (Tx2) Write Enhanced base + 3 STAT1 Read Enhanced base + 4 CMD1 Write Enhanced base + 4 STAT2 Read Enhanced base + 5 CMD2 Write Enhanced base + 5 Not Used (DMA Rx) Read Enhanced base + 6 Not Used (DMA Tx) Write Enhanced base + 6 Received Word Status Read Enhanced base + 7
Bit assignments for this read only register are as follows:
Bit Description 7 1 always CMD2 ready 6 1 always STAT2 ready 5 1 always CMD1 ready 4 1 always STAT1 ready 3 0 always Tx2 ready 2 0 always Rx2 ready 1 Tx1 ready 0 = DMA Tx in progress, else 1 0 Rx1 ready 0 = DMA Rx in progress, else 1
Note: The part is usually ready to accept commands and data. However, it is not recommended to read or write data from the FIFO's during a DMA transfer.
Bit assignments for this read only register are as follows:
Bit Description 7 1 = DMA timeout 6 0 (Always) 5 0 (Always) 4 0 (Always) 3 1 = DMA TC 2 1 = Error status 1 1 = Transmit FIFO level reached 0 1 = Receive FIFO level reached
Note: Reading this register will clear the DMA TC and timeout interrupts automatically. The error status interrupt will be cleared upon reading the appropriate registers with the Get Error Status (12h) command. The Tx/Rx level reached interrupts will only be cleared when the FIFO levels go below the values specified by the Set FIFO Trigger Levels (0Bh) command.
Note: Wait states should be enabled for 16-bit (word) data transfers. See the Set Clock Prescaler (23h) Command.
Note: Wait states should be enabled for 16-bit (word) data transfers. See the Set Clock Prescaler (23h) Command.
Bit Description 7 not used 6 not used 5 High Byte break interrupt 4 framing 3 parity 2 Low Byte break interrupt 1 framing 0 parity
Step 1: Determine if any of the COM1 through COM4 ports is an ESP Communications Accelerator Version 2.0 port. This can be done by searching through the valid Master/Slave I/O addresses as follows:
Step 2: Repeat the above steps for all master I/O addresses and any slaves that are associated with a found master.
Step 3: Do the 'normal' 16550 initialization.
Step 4: Enable the FIFOs at the UART FIFO Control Register, FCR, bit 0.
Note: Due to a problem with the receive trigger level enable in UART mode the DMA mode select bit (bit 3) should also be set when enabling the FIFO's.
Step 5: Scale the UART trigger levels using the Set Mode (10h) command CMD2, bit 7. You can significantly reduce the number of interrupts by scaling the trigger levels to 1, 64, 256, and 512 bytes. While issuing the Set Mode command, CMD2 bit 1 should be set to ensure that the Compatibility Mode UART FIFOs are enabled.
Step 6: Issue the Set Flow Control Type (08h) command for the type of flow control desired.
Step 7: Issue the Set Rx Flow Control (0Ah) command to set the flow control levels.
Step 8: For Hardware Flow Control, set the appropriate bits (0 and 1) in the UART Modem Control Register (MCR) to turn on RTS and DTR.
Step 9: Set the bit/s rate. If 230,400 bit/s is desired, set the bit/s to 115,200 and issue the Set UART Clock ESI Prescaler (23h) command with a value of 01.
Step 10: The interrupt service routine should probably be altered to take advantage of transmit and receive buffers that are 1KB each.
Note: For software flow control, there are two ESI commands available that flow on and off the local transmitter.
ESPCA F S Rxxx:y Pxxx:z where: F enables all ESP2 FIFOs. S disables the configuration read from the card. Rxxx:y controls RTS/CTS flow control at a specifed address (xxx). Set y to "+" to turn flow control on, "-" to turn it off. Pxxx:z sets the UART clock at a specified address (xxx) and prescaler value (z) defined as follows: 0 1.8432 MHz 115,200 bps 1 3.6864 MHz 230,400 bps 2 7.3728 MHz 460,800 bps 3 14.7456 MHz 921,600 bps
An example of the command is as follows:
ESPCA F S R240:+ P240:1