Instructions: You should do this homework individually. You should staple multiple pages together. Make sure you list your section number and name and email address on the first page.
First contact TA is Shengnan Wang (shengnan@cs.wisc.edu)
Assume a memory’s addressability is 32 bits. What does that tell you about the size of the MAR and MDR?
Say we have a memory consisting of 256 locations, and each
location contains 16 bits.
a. How many bits are required for the address?
b. If we use the PC-relative addressing mode, and want to allow control transfer between instructions 15 locations away, how many bits of a branch instruction are needed to specify the PC-relative offset?
c. If a control instruction is in location 3, what is the PC-relative offset of address 12. Assume that the control transfer instructions work the same way as in the LC-3.
If we increase the number of registers that we can specify in the LC-3 ADD instruction to 32, do you see any problem with that? Explain.
a. How might one use a single LC-3 instruction to move the value in R3 into R1?
b. Write an LC-3 instruction that clears the contents of R3.
c. Using only one LC-3 instruction and without changing the contents of any register, how might one set the condition codes based on the value that resides in R1?
d. The LC-3 has no subtract instruction. How could one perform the following operation using only three LC-3 instructions:
R1 <- R3 - R2
e. Is there a sequence of LC-3 instructions that will cause the condition codes at the end of the sequence to be N = 1, Z = 1, and P = 0?
If the control is redirected to location 0x4444 after the execution of the following instructions, what should have been the relationship between R1 and R2 before these instructions were executed? (Please show your steps for solving this problem to receive full credit)
Address Instruction
0x4400 1001 011 001 111111
0x4401 0001 011 011 100001
0x4402 0001 011 010 000011
0x4403 0000 100 001 000000
We would like to have an instruction that does nothing. Many ISAs actually have an opcode devoted to doing nothing. It is usually called NOP, for NO OPERATION. The instruction is fetched, decoded, and executed. The execution phase is to do nothing! Which one of the following three instructions could be used for NOP and have the program still work correctly?
What does the ADD
instruction do that the others do not do?
The LC-3 does not have an opcode for logical function OR. That is, there is no instruction in the LC-3 ISA that performs the OR operation. However, we can write a sequence of instructions to implement the OR operation. The four instruction sequence below performs the OR of the contents of register 1 and register 2 and puts the result in register 4. Fill in the two missing instructions so that the four instruction sequence will do the OR operation.
1) 1001 011 001 111111
2)
3) 0101 110 011 000 101
4)
The PC contains 0x3010. The following memory locations contain values as shown:
0x3050: 0x
0x
0x
0x
The following
three LC-3 instructions are then executed, causing a value to be loaded into R5.
What is that value? (Show your steps to receive full credit)
0x3010 1110 0110 0011 1111
0x3011 0110 1000 1100 0000
0x3012 0110 1011 0000 0000
We could
replace the three instruction sequence with a single instruction. What is it?
The purpose of this problem is to get you setup with the LC-3 simulator, which will be important for subsequent homeworks. You can get the LC-3 simulator in one of the following ways:
After opening
the LC-3 simulator, please report the following: