CS/ECE 752 Advanced Computer Architecture I Fall 2006 Section 1 Instructor David A. Wood and T. A. Arini Balakrishnan URL: http://www.cs.wisc.edu/~david/courses/cs752/Fall2006/

Homework 3 // Due at Lecture Tue, Nov 27

Problem 1 (15 points)

Construct and fill the following tables:
1) ROB
2) Reservation Stations
3) Map Table
4) Free List
5) CDB
  for an R10K processor executing the following code (note: the destination operand is always on the right):

loop: 	ldf X(r1),f1
  	ldf X(r2),f2
	mulf f1,f2, f0
	addf f4, f0, f4
	stf f0,X(r1)
	addi r1,4,r1
	addi r2,4,r2
	slt r1,r3,r4
	BNQZ r4,loop

Assumptions:
1) The processor can retire one instruction at a time.
2) The processor can issue one instruction at a time.
3) Floating Point, load and store operations take 3 cycles to execute.
4) Integer operations take 1 cycle to execute.
5) Function units are pipelined.
6) Branch prediction is perfect and the above loop is repeated twice.
7) There are only 14 physical registers and they can be used to store floating point and integer values.
8) There are only 8 ROB slots available and 5 reservation stations.

Tables status at the beginning of cycle 3:
ROB 
ht 	#	Inst		T	Told	S	X	C
h	1	ldf X(r1),f1	PR#7	PR#2	c2	c3	c6
	2	ldf X(r2),f2	PR#8	PR#3	c3
	
Reservation Stations
#	FU	Busy	op	T	T1	T2
1	ALU	N	
2	L/S1	Y	
3	L/S2	N	ldf	PR#8	-	PR#5+
4	FP1	N
5	FP2	N

Map Table
f0	PR#1+
f1	PR#7
f2	PR#8
f4	PR#14+
r1	PR#4+
r2	PR#5+
r3	PR#6+
r4	PR#13+

Free List
PR#9,PR#10,PR#11,PR#12

Reference: The MIPS R10000 SuperScalar MicroProcessor By Kenneth C. Yeager

Problem 2 (15 points)

The following code segment, consisting of six instructions, needs to be executed 100 times 
for the evaluation of vector arithmetic expression: D(I)= A(I)+B(I)*C(I) 
for 0<=I<100:
	load r1, B(i)	// dest is always on the right
	load r2, C(i)
	mul r1,r2, r1
	load r3, A(i)
	add r3,r1,r3
	sto r3, D(i)
where r1,r2, and r3 are CPU registers. Assume four cycles for each load or store, two cycles for add, 
and eight cycles for multiply on either a uniprocessor or a single PE in an SIMD machine.

1. Calculate the total number of CPU cycles needed to execute the above code 100 times on an in-order uniprocessor, ignoring all other delays.
    
2. Rewrite this code using the vector extensions to the MIPS ISA. Assume the maximum vector length (vector register length) is 64 (yes, 64!).
    
3. Consider executing this code on a pipelined vector processor with one load pipe, one store pipe, one multiply pipe, and one add pipe. The pipes have latencies of 20, 10, 8, and 5 cycles to the first result and can sustain one result per cycle. State any other assumptions that you must make. Assume that there is NO chaining. What is the speedup gain of the vector processor over the uniprocessor one?  
    
4. Redo part c, but assuming that chaining allows the result of one vector pipe to be forwarded to another with a 2 cycle delay. What is the speedup over the unchained vector processor?

Problem 3 (5 points)

H&P Problem 5.7

Problem 4 (7 points)

H&P Problem 5.18

Problem 5 (8 points)

Consider a computer that implements paged virtual memory with 50-bit virtual addresses (i.e., the top 15 bits of the 64-bit address must be the same), 41-bit physical addresses, 16K-byte pages, and 8-bit address space identifiers.

Assume it uses a 128K-byte L1 data cache with two-way set-associativity, LRU replacement, 64-byte blocks, and write-back.

(a) Let the data cache be accessed logically after address translation. Exactly which bits need to stored in a block's tag? What other bits (e.g., state bits) need to be stored with each block?

(b) Repeat part (a) assuming instead that the data cache is accessed logically before address translation and need not be flushed on most context switches.

Problem 6 (15 points)

Using a CS Unix/Linux machine, download and install the Simplescalar v 3.0 Source code from http://www.simplescalar.com/. Descriptions for the Integer Benchmarks and Floating Point Benchmarks can be found at the Standard Performance Evaluation Corporation's website. To run the benchmarks, the command line arguments for each benchmark must be specified after the executables name. The command line options necessary for each benchmark are at /unsup/spec2000/benchspec/benchmark.cmdlines. From there, the associated Alpha executables and data files for the integer benchmarks and floating point benchmarks are in the CINT2000 and CFP2000 directories respectively.

a) The benchmarks have initialization phases at the beginning of their execution that run only once. Researchers tend to avoid collecting data from this region because it is not representative of the entire program. Choose a benchmark and find the likely end of its initialization period by observing its IPC in sim-outorder while it executes. Describe which benchmark you chose, your methodology, and your results. You might consider fast-forwarding to a certain instruction and limiting the number of instructions run at any one time. Assume the initialization period to be a factor of at least 10 million.

b) Using the performance of gcc in sim-outorder Use the following basic configuration:

Two Level Cache:
	L1 instruction cache: 16K 2-way set associative with 64 byte lines.
	L1 data cache: 32K 4-way set associative with 32 byte lines. 
	L2 unified cache: 256K 4-way set associative unified L2 cache with 64 byte lines.
	Branch prediction: use the default branch prediction settings.

report the IPC and the cache hierarchy miss rates if:

Two Level Cache using LRU replacement policy:
	L1 instruction cache: 16K 2-way set associative with 64 byte lines.
	L1 data cache: 32K 2-way set associative with 32 byte lines. 
	L2 unified cache: 256K 8-way set associative unified L2 cache with 128 byte lines.
	Branch prediction: use the default branch prediction settings.