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Homework 4 // Due at the final exam, Monday December 18thProblem 1 (20 points)The simple, bus-based multiprocessor illustrated below represents a commonly-implemented symmetric shared-memory architecture. Each processor has a single, private cache with coherence maintained using the snooping coherence protocol of Figure 6.12. Each cache is direct-mapped, with four blocks each holding two words. To simplify the illustration, the cache address tag contains the full address and each word shows only two hex characters, with the least significant word on the right. The coherence states are denoted M, S, and I for Modified, Shared, and Invalid.
For each subproblem below, assume the initial cache and memory state as illustrated in Figure . Each subproblem specifies a sequence of one or more CPU operations of the form: P#: <op> <address> [ <-- <value> ] Where P# designates the CPU (e.g., P0), <op> is the CPU operation (e.g., read or write), <address> denotes the memory address, and <value> indicates the new word to be assigned on a write operation. What is the final state (i.e., coherence state, tags, and data) of the caches and memory after the given sequence of CPU operations has completed? Show only the blocks that change, e.g., P0.B0: (I, 120, 00 01) indicates that CPU P0’s block B0 has the final state of I, tag of 120, and data words 00 and 01. Also, what value is returned by each read operation?
Problem 2 (10 points)
H&P Problem 6.29 (3rd edition)
Problem 3 (10 points)Considering Micron memory chips, compare between SDRAM-133, DDR-266, and DDR2-533 in the following aspects: a) Maximum Bandwidth. b) Memory Structure (Banks, Rows, Columns, Width). c) The minimum time to Zero Memory. Note: Use the following product line for all of the chips: 256MB (64*4), Lead Free with 60-ball Pin Count.
Problem 4 (10 points) H&P Problem 7.7a-d (3rd Edition), but only do it for the small disk. |
