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CS 757 Parallel Computer Architecture
Spring 2012 Section 1
Instructor Mark D. Hill
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TSO, etc.
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Outline

* (SC Formalism)
* TSO Motivation
* TSO Formalism
* Implementing TSO
* RMW & FENCES
* 4Ps
* (Relaxed Forecast)


SC Formalism

* Program order <p  -- total for each processor; partial overall
* Memory order <m -- total for all memory operations

Address a and b may be the same or different

* If L(a) <p L(b) ==> L(a) <m L(b)
* If L(a) <p S(b) ==> L(a) <m S(b)
* If S(a) <p S(b) ==> S(a) <m S(b)
* If S(a) <p L(b) ==> S(a) <m L(b)

Value of L(a) = Value of MAX over <m of {S(a) | S(a) <m L(a)}

Value of the "last" store to the same address.
	
	Operation 2
Op 1	Load	Store

Load	X	X
Store	X	X

X == Op1 <p Op2 ==> Op1 <m Op2

SC exection -- one execution okay
SC system -- only SC execution permitted


TSO Motivation

Recall...
                /* initial A = B = 0 */
                  P1                        P2
                A = 1;                  B = 1
                r1 = B;                 r2 = A;

Allow fourth outcome: PC, TSO, x86
Why do this?

        Allows FIFO write buffers
        Does not astonish programmers (too much)

This example still works:

/* initial A = B = flag = 0 */
                  P1                P2
                A = 1;          while (flag == 0); /* spin */
                B = 1;          print A;
                flag = 1;       print B;

For SC and TSO: A = B = 1


TSO Formalism

* If L(a) <p L(b) ==> L(a) <m L(b)
* If L(a) <p S(b) ==> L(a) <m S(b)
* If S(a) <p S(b) ==> S(a) <m S(b)
* If S(a) <p L(b) ==> not contrained -- FIFO write buffers

Value of L(a) = Value of MAX over <m of {S(a) | S(a) <m L(a) or S(a) <p L(a)}

	Operation 2
Op 1	Load	Store

Load	X	X
Store	B	X

B == TSO bypass



Implementing TSO

(1) Do write-invalidate cache coherence

(2) Add FIFO write buffer

(3) Each processor COMMITS loads to its cache store to its write buffer
in program order.

(3) Okay to SPECULATE.


Show -- railroad with writebuffers -- Figure 4.4

Point to Sewell et al.


Implementing Atomic RMW
* As IF flushed WB and stopped rest of system
* Don't need to stop others as long as hold M permission for read-to-write
* Since load-store together, store can't pass stores, RMW load-store can't pass anything

FENCE

Don't want TSO execution with r1==0 and r2==0? Add FENCES
Example

          A = 1     B = 1
	  FENCE     FENCE
	  r1 = A    r2 = B

Can implement fence by flushing writebuffer
Okay implementation since FENCEs rare
FENCES more important for relaxed models

In Summary
	
		Operation 2
Op 1	Load	Store	RMW	FENCE

Load	X	X	X	X
Store	B	X	X	X
RMW	X	X	X	X
FENCE	X	X	X	X

X == Op1 <p Op2 ==> Op1 <m Op2
B == TSO bypass


Want 4Ps:

* Programmability: EZ to program -- SC yes; TSO close
* Performance: faciliates good performance (or low cost) -- Okay
* Portable -- yes
* Precision -- yes for SC and TSO, x86-TSO

Show vend diagrams -- Figure 4.5
* executions
* implementations
* SC, TSO than MC1 and MC2

Relaxed Memory Models Motivation

/* initially all 0 */
		  P1			    P2
		A = 1;			while (flag == 0); /* spin */
		B = 1; 			r1 = A;
		flag = 1; 		r2 = B;


* Recall SC has
   Each processor generates at total order of its reads and writes
   R-->R, R-->W, W-->W, & W-->R)
   That are interleaved into a global total order

* (Most) Relaxed Models
   TSO "PC": Relax ordering from writes to (other proc's) reads
   RC: Relax all read/write orderings (but add “fences”)

But many (most) order NOT necessary!

Why not just enforce necessary orders?