.nr PD 1v
.nr PS 12
.nr VS 18
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.TL
OCT Tools Demonstration
.AU
Paul B. Cohen
.AI
Massachusetts Microelectronics Center
.LP
One of the tasks performed by the staff of the Microelectronics Center
is the aquisition and evaulation of new VLSI CAD tools. When we come
across a tool which we feel will be useful to the consortium faculty,
we learn to use that tool so that we may prepare internal courses and
instructional materials. Attendance at these courses helps  the
faculty to make an informed decision regarding the use of the tools in
their classes or research. In addition, by using the tools for our own
chip development projects, we are better able to provide support to
those who choose to adopt the tools.
.LP
A case in point is the OCT tool suite, from the University of
California at Berkeley. These tools are based on logic synthesis, with
design entry in a high level language, schematic capture, or a
combination of the two. Layouts may be automatically generated or
created with the graphical layout editor.
.LP
{\fI\s+2Type octdemo and hit return.\s-2\fR} Let's take a look at
the OCT tool suite.
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This text represents the description of a 3 to 8 decoder in B-D-S, the
high level language used in the OCT tools. The program B-D-SYN converts
this description Berkeley Logic Interchange Format, or B-LIF.
.LP
The B-LIF description is then read into the logic optimizer, called
M-I-S 2. While this is running, let's take a closer look at the high
level description of the decoder.
.IP
.ps 10p
.vs 12p
[The decoder description is reproduced here for reference.]
.sp
model decode out<7:0> = sel<2:0>;
.br
routine main;
.br
	out = (ZXT {width=8} 1) sl0 sel;
.br
endroutine;
.br
endmodel;
.LP
{\fI\s+2Move the cursor to the BDS window, the first line will be
highlighted - autoraise is ON\s-2\fR} The first line of this file
defines the 8 output bits, described in vector notation as OUT 7
through zero, as a function of the 3 input bits. The inputs, also in
vector notation, are named SEL 2 through zero.
.LP
{\fI\s+2(ZXT {width=8} 1) will become highlighted\s-2\fR} This portion of
the file describes the number 1, zero extended to a total width
of 8 bits. The keyword Z-X-T indicates zero extend.
.LP
{\fI\s+2Point to sl0 sel\s-2\fR} The shift left fill zero command
(abbreviated S-L-zero) performs a logical shift by the number of bits
indicated by the S-E-L input bits.
.LP
Since B-D-S describes only combinational logic,
the SHIFT function describes a logical shift as opposed to a
sequential shift. We will see the effect of this shortly when we
examine the simulation results.
.LP
{\fI\s+2Move the cursor to the misII window, near the read-library
command - autoraise is ON\s-2\fR} M-I-S 2 is nearly complete. Note
that it has read in the M-S-U cell library, from Mississippi State
University, and is mapping the optimized logic into the available
cells.
.LP
{\fI\s+2Two new windows will appear. Move the cursor to the normal
size place and route window\s-2\fR} In this window, we are starting
WOLFE, the OCT interface to the TIMBERWOLF-S-C standard cell place and
route software.
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{\fI\s+2Move the cursor to the simulation window\s-2\fR} In this
window we have run B-D-SIM, the multi-level simulator in the OCT tool
suite. Let's take a look at the results.
.LP
We have chosen to display the S-E-L inputs in HEX format, thus the letter H
preceeeding the value. The output bits, are
displayed in BINARY, with  the most significant bit, OUT 7 on the left.
.LP
{\fI\s+2Point to H0 near the top of the sim window\s-2\fR} At the
start of this simulation, we set the 3 S-E-L input bits to zero. We
expect, and in fact see, that bit OUT zero is at logic 1, while the
remaining 7 bits are at logic 0. We then
increment the S-E-L inputs through all 8 possible states.
.LP
{\fI\s+2Place the cursor over the H0 near the top of the sim
window\s-2\fR} We can better
understand the original B-D-S file if we take another look at the
simulation results.
Looking at the output for S-E-L equal to 0,
note that we have the binary number 1, zero extended to a total of 8
bits. As we change the value on the S-E-L inputs, notice that that
sole logic 1 is shifted towards the left
the number of bit positions, zero through 7, as indicated by the S-E-L
inputs. 
.LP
{\fI\s+2Move the cursor to the Wolfe window\s-2\fR} At this point, the
layout of the decoder is nearly complete.
.LP
The program WOLFE takes the OCT description of the standard cells and
the interconnection of those cells and converts it to the ASCII files
needed to run TIMBERWOLF-S-C. WOLFE then invokes TIMBERWOLF to create
the final layout of the circuit.
.LP
{\fI\s+2When the sim and wolfe windows disappear, a VEM console window
and graphics window will appear. The layout will be displayed in the
VEM graphics window.\s-2\fR} We have started VEM, the graphics editor
for designs using the OCT data representation. From this window,
called the VEM console window, we can open graphics windows on
different representations of the design. If we think about the gates
needed to implement the decoder, we expect to see 3 inverters and 8 3
input nor gates, Those familiar with CMOS design will, in fact, see
that this is the case.
.LP
{\fI\s+2The VEM windows will disappear, and a new VEM window will open
at the same time as a new xterm running misII. A schematic of the
decoder will also appear. \s-2\fR} Using the schematic capture
capabilities of VEM, we have created a schematic of the logic which
corresponds to the layout. Note the 3 inverters to generate the
complement of the S-E-L inputs and the 8 nor gates to decode the
value.
.LP
{\fI\s+2With the cursor in the layout window, type: "sel<0>", then
click the middle mouse button. Click again over the select-net command
on the Selection page of the menu\s-2\fR} Just as a quick sanity
check, if we select the net S-E-L zero, we expect to see that net
connect to 1 inverter and 4 nor gates. We can see from the highlighing
that this is so.
.LP
{\fI\s+2type CTRL-u to remove the highlighting\s-2\fR} If we had
preferred, we could have used VEM to draw the schematic and then
synthesized the layout with the schematic as a starting point. Let's
do that now.
.LP
{\fI\s+2Move the mouse over the MIS window, over the
line that says "ro decode:schematic"\s-2\fR} We will use M-I-S 2 again
to map the schematic into the M-S-U cells. Notice the first line of
the file. R-O is an abbreviation for READ OCT, and we have provided
the schematic name as an argument. As before, M-I-S 2 will read in the
M-S-U library and map the logic into the available cells. I should
point out that all of these programs are running as we speak, to give
you an idea of the runtimes involved.
.LP
{\fI\s+2Wait a few seconds for the sim and wolfe windows to
re-appear. Move to the wolfe window\s-2\fR} As before, we will start
the place and route program while we look at the simulation. It is
important to note that at this point, the same commands used to control the
earlier place and route are being used here. The only difference is in
the input we provided to M-I-S 2.
.LP
{\fI\s+2Move the cursor to the sim window\s-2\fR} We have once again
used B-D-SIM to simulate the decoder. This time, however, we have
indicated B-D-SIM should simulate the schematic version of the
decoder. The control file used to run the simulation is the same file
we used earlier. As we expect, the simulation results are the same as
before.
.LP
I would like to point out that the simulation on the schematic level
description of the logic could have been done before we ran M-I-S 2.
We used M-I-S 2 only to map the schematic into the M-S-U library this
time.
.LP
We could have used M-I-S-2 to map the logic description into either
the gate matrix library or the P-L-A library. The specific tools
involved in generating gate matrix or P-L-A layout are different, but
the concept of working at a high level and synthesizing the layout is
similar.
.LP
For example, had we chosen a gate matrix implementation, we would have
used genie to optimize the matrix, then electra to actually do the
layout and wiring. Sparcs would then be used to compact the layout and
assure compliance with the layout rules.
.LP
The P-L-A synthesis path is similar, but octopus would have been used
to do the layout and wiring rather than electra.
.LP
It is interesting
to note that if we changed the S-L-zero keyword in the original B-D-S file to
S-L-1, we would change the logic to generate a bar graph type output,
where all bits less than or equal to the S-E-L value would be high.
.LP
I'd like to point out that
the program controlling this demo is actually running the individual
tools as we speak, to give you an idea of the run times involved.
.LP
{\fI\s+2Wait for WOLFE to finish, and VEM will start. The schematic
and the layout generated from the scheamtic will also appear.\s-2\fR}
We can now look at the final layout of the decoder once again, this
time with the schematic as the input description. We can notice there
are slight differences in the order of the cells, but the overall
quality of the layout is independent of the input format.
.LP
{\fI\s+2The script will terminate  5
seconds after the VEM windows close.\s-2\fR}.