Berkeley Logic Interchange Format (blif)

University of California Berkeley

October 28, 1988

The goal of blif is to describe a Boolean network in textual form. A Boolean network is a representation of an arbitrary combinational logic network, and is an acyclic directed graph with a logic function attached to each node. Each node in this representation has a single output. Therefore, each net (or signal) has only a single driver, and we can therefore name either the signal or the gate which drives the signal without ambiguity.

In this section, angle-brackets surround nonterminals, and vertical bar separates choices in a pseudo-BNF style. Bdsyn uses only the logic-gate construct of blif. Bdsyn uses the the keywords .module, .inputs, .outputs, .end, and .names. The module-reference construct of blif is not implemented.

1 Modules

A module is declared by:

    .module <decl-module-name>
    .inputs <decl-input-list>
    .outputs <decl-output-list>
    <logic-gate> | <pla-reference> | <module-reference> | <timing-constraints>
             .
             .
             .
    <logic-gate> | <pla-reference> | <module-reference> | <timing-constraints>
    .end

decl-module-name is a string giving the name of the module.

decl-input-list is a white-space-separated list of strings (terminated by the end of the line) giving the formal parameters for the module being declared. If this is the last or only module, then these signals can be identified as the primary inputs of the circuit. Multiple .inputs lines are allowed, and the lists of inputs are merely concatenated.

decl-output-list is a white-space-separated list of strings (terminated by the end of the line) giving the formal parameters for the module being declared. If this is the last or only module, then these signals can be identified as the primary outputs of the circuit. Multiple .outputs lines are allowed, and the lists of inputs are merely concatenated.

It is expected that a blif parser may allow the .inputs and .outputs statements to be optional. If they are not specified, the primary inputs can be inferred from the signals which are not the outputs of any other logic block, and the primary outputs can be inferred from the signals which are not the inputs to any other blocks. This makes the serious assumption that no primary output is used as an intermediate signal. Also, these assumptions are only useful for the “root” module. Subcircuits are invoked with positional arguments and hence the specified order for the inputs is significant in a subcircuit.

The keyword .end is optional, and is implied at the end of the file.

Anywhere in the file, a ‘\’ (backslash) as the last character on a line indicates concatenation of the subsequent line to the current line.

2 Logic Gates

A logic-gate is:

    .names <in-1> <in-2> ... <in-n> <output>
    <single-output-cover>

single-output-cover is an n-input, 1-output PLA description of the logic function corresponding to the logic gate. {0, 1, –} is used in the “input plane” and {0, 1, –, ~} is used in the “output plane”. The logic gate can have only its ON-set specified with 1’s in the “output plane”, or can also have a DC-set and an OFF-set specified with -’s or 0’s in the “output plane”. ~ means no connection. For a more complete description of the PLA input format, see espresso(5).

3 Module (subcircuit) references

A module-reference is

    .subckt <module-name> <input-list> <output-list>

module-name gives the name of a module being included. It must be previously defined in the file. input-list are the actual parameters and are matched one-to-one with the corresponding decl-input-list inside the module declaration. Likewise, output-list are the actual parameters and are matched one-to-one with the corresponding decl-output-list inside the module declaration.

input-list and output-list are white-space separated sequence of tokens ending with the end of the line. A “/” may be used to separate input-list from output-list. The end of input-list and the start of output-list is, however, always inferred from the number of inputs and outputs in the module declaration (i.e., from decl-input-list and decl-output-list of the module which is being called).

If both input-list and output-list are not given, then the formal parameters within the module declaration become the actual parameters. It is an error if the input-list and output-list are given and the number of inputs or outputs does not match the “call” and the definition.

4 PLA References

A pla-reference is

    .pla <pla-name> <input-list> <output-list>

pla-name gives the name of a file containing a pla description in the format understood by espresso(5). input-list and output-list are matched 1 for 1 with the inputs and outputs of the PLA (which, for arcane reasons are given via .ilb and .ob keywords within the PLA). Similar to .subckt, a “/” may separate the input-list and the output-list and if both are missing, the formal parameters become the actual parameters.

5 Timing Constraints

A timing-constraints is one or more of

    .input_arrival <in-name> <rise> <fall>
    .output_required <out-name> <rise> <fall>
    .input_drive <in-name> <rise> <fall>
    .output_load <out-name> <load>
    .default_input_arrival <rise> <fall>
    .default_output_required <rise> <fall>
    .default_input_drive <rise> <fall>
    .default_output_load <load>

rise, fall, drive, and load are all floating point numbers giving the rise time, fall time, input drive, and output load. input arrival sets the input arrival time for the input in-name. output required sets the output required time for the output out-name. input drive sets the input drive for the input in-name. input load sets the output load for the output outname. defualt input arrival, default output required, default input drive, defualt output load set the corresponding default values for all the inputs/outputs whose values are not specifically set. There is no unit for all the timing and loading numbers. Special attention should be given when specifying and interpreting the values.